AD9243AS ,Complete 14-Bit, 3.0 MSPS Monolithic A/D ConverterSPECIFICATIONS otherwise noted)Parameter AD9243 UnitsRESOLUTION 14 Bits minMAX CONVERSION RATE 3 MH ..
AD9244BST-40 ,14-Bit, 40/65 MSPS Monolithic A/D ConverterAPPLICATIONSAGND CML VR VREF REF REF DRGNDCommunications Subsystems (Microcell, Picocell)SENSE GNDM ..
AD9244BST-65 ,14-Bit, 40/65 MSPS Monolithic A/D Converterfeaturesthe DC accuracy and temperature drift requirements of thea separate digital output driver s ..
AD9244BST-65 ,14-Bit, 40/65 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, CLKVDD=3V, DRVDD = +3.0 V, f = 65 MSPS (-65) or 40MSPS (-40), INPUT RA ..
AD9244BSTZ-40 ,14-Bit 40/65 MSPS IF Sampling Analog-To-Digital ConverterSPECIFICATIONS External Reference, Differential Analog Inputs, unless otherwise noted.)Test AD9 ..
AD9244BSTZ-65 ,14-Bit 40/65 MSPS IF Sampling Analog-To-Digital ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD9244 is a monolithic, single 5 V supply, 14-bit, Low Po ..
ADS7822E/250 ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterELECTRICAL CHARACTERISTICS: +V = +2.7VCCAt –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 75kHz, and f ..
ADS7822E/2K5 ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterSBAS062C–JANUARY 1996–REVISED AUGUST 2007This integrated circuit can be damaged by ESD. Texas Instr ..
ADS7822P ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterSBAS062C–JANUARY 1996–REVISED AUGUST 2007This integrated circuit can be damaged by ESD. Texas Instr ..
ADS7822PB ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)ADS7822 UNITV +6 V ..
ADS7822U ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterMaximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
ADS7822U/2K5G4 ,12-Bit, 200kSPS Micro Power Sampling Analog-To-Digital Converter 8-SOIC -40 to 85.(2) Performance grade information is marked on the reel.(1)ABSOLUTE
AD9243AS
Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV.A
Complete 14-Bit, 3.0 MSPS
Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Monolithic 14-Bit, 3 MSPS A/D Converter
Low Power Dissipation: 110 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio:79.0 dB
Spurious-Free Dynamic Range:91.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Lead MQFP
PRODUCT HIGHLIGHTSThe AD9243 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-lead Metric Quad
Flatpack.
Low Power and Single SupplyThe AD9243 consumes only 110 mW on a single +5 V power
supply.
Excellent DC Performance Over TemperatureThe AD9243 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low NoiseThe AD9243 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input RangeThe versatile onboard sample-and-hold (SHA) can be configured
for either single ended or differential inputs of varying input spans.
Flexible Digital OutputsThe digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
PRODUCT DESCRIPTIONThe AD9243 is a 3 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9243 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9243 performs well in communication systems employ-
ing Direct-IF Down Conversion since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 1.5MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
*Patents pending.
AD9243–SPECIFICATIONS
DC SPECIFICATIONSACCURACY
INTERNAL VOLTAGE REFERENCE
POWER SUPPLIES
POWER CONSUMPTION
NOTESVREF =1 V.Including internal reference.Excluding internal reference.Load regulation with 1 mA load current (in addition to that required by the AD9243).
Specification subject to change without notice.
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, fSAMPLE = 3 MSPS, VREF = 2.5 V, VINB = 2.5 V, TMIN to TMAX unless
otherwise noted)
AC SPECIFICATIONSSpecifications subject to change without notice.
DIGITAL SPECIFICATIONSLOGIC OUTPUTS (with DRVDD = 5 V)
LOGIC OUTPUTS (with DRVDD = 3 V)
Specifications subject to change without notice.
AD9243
(AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, fSAMPLE = 3 MSPS, VREF = 2.5 V, AIN = –0.5 dBFS, AC Coupled/
Differential Input, TMIN to TMAX unless otherwise noted)
(AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)
AD9243
ABSOLUTE MAXIMUM RATINGS*VINA, VINB
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
SWITCHING SPECIFICATIONSNOTESThe clock period may be extended to 1 ms without degradation in specified performance @ +25°C.
Specifications subject to change without notice.
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, CL = 20 pF)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Figure 1.Timing Diagram
THERMAL CHARACTERISTICSThermal Resistance
44-Lead MQFP
θJA = 53.2°C/W
θJC = 19°C/W
ORDERING GUIDE*S = Metric Quad Flatpack.
PIN CONNECTIONS
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
TEMPERATURE DRIFTThe temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTIONThe specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTERAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAYAperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIOS/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDRThe ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
PIN DESCRIPTION
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
ZERO ERRORThe major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERRORThe first code transition should occur at an analog value
1/2LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal differ-
ence between first and last code transitions.
AD9243
Typical Differential AC Characterization Curves/Plots
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5V, fSAMPLE
= 3.00 MSPS, TA = +258C, Differential Input)Figure 2.SINAD vs. Input Frequency
(Input Span = 5 V, VCM = 2.5 V)
Figure 5.SINAD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
Figure 8.THD vs. Sample Rate
(fIN = 1.5MHz, AIN = –0.5dBFS,
VCM = 2.5 V)
Figure 3.THD vs. Input Frequency
(Input Span = 5V, VCM = 2.5 V)
INPUT FREQUENCY – Hz
THD – dB
–100100k1M20M10M
–60Figure 6.THD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
Figure 9.Single Tone SFDR
(fIN = 1.5MHz, VCM = 2.5 V)
Figure 4.Typical FFT, fIN = 500kHz
(Input Span = 5V, VCM = 2.5 V)
Figure 7.Typical FFT, fIN = 1.50MHz
(Input Span = 2V, VCM = 2.5 V)
Figure 10.Dual Tone SFDR
(f1 = 0.95 MHz, f2 = 1.04 MHz,
VCM = 2.5 V)
Other Characterization Curves/Plots
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5V, fSAMPLE = 3.00 MSPS, TA = +258C,
Single-Ended Input)
CODE
INL – LSB
1.0Figure 11.Typical INL
(Input Span = 5 V)
Figure 14.SINAD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
Figure 17.SINAD vs. Input Frequency
(Input Span = 5 V, VCM = 2.5 V)
Figure 12.Typical DNL
(Input Span = 5 V)
Figure 15.THD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
Figure 18.THD vs. Input Frequency
(Input Span = 5 V, VCM = 2.5 V)
Figure 13.“Grounded-Input”
Histogram (Input Span = 5 V)
Figure 16.CMR vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
Figure 19.Typical Voltage Reference
Error vs. Temperature
AD9243Therefore, the equation,
VCORE = VINA – VINB(1)
defines the output of the differential input stage and provides the
input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF ≤ VCORE ≤ VREF(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9243. The
power supplies bound the valid operating range for VINA and
VINB. The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V(3)
AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9243, see
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations.
ANALOG INPUT OPERATIONFigure 21 shows the equivalent analog input of the AD9243
which consists of a differential sample-and-hold amplifier (SHA).
The differential input structure of the SHA is highly flexible,
allowing the devices to be easily configured for either a differen-
tial or single-ended input. The dc offset, or common-mode
voltage, of the input(s) can be set to accommodate either single-
supply or dual supply systems. Also, note that the analog inputs,
VINA and VINB, are interchangeable with the exception that
reversing the inputs to the VINA and VINB pins results in a
polarity inversion.
Figure 21.AD9243 Simplified Input Circuit
INTRODUCTIONThe AD9243 utilizes a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last stage, consists of a low resolution flash A/D
connected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ-
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er-
rors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
The AD9243 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEWFigure 20, a simplified model of the AD9243, highlights the rela-
tionship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top
of the resistor ladder in a flash A/D converter, the value VREF
defines the maximum input voltage to the A/D core. The minimum
input voltage to the A/D core is automatically defined to be –VREF.
Figure 20.AD9243 Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the difference
of the voltages applied at the VINA and VINB input pins.
The input SHA of the AD9243 is optimized to meet the perfor-
mance requirements for some of the most demanding commu-
nication, imaging, and data acquisition applications while
maintaining low power dissipation. Figure 22 is a graph of the
full-power bandwidth of the AD9243, typically 40 MHz. Note
that the small signal bandwidth is the same as the full-power
bandwidth. The settling time response to a full-scale stepped
input is shown in Figure 23 and is typically 80 ns to 0.0025%.
The low input referred noise of 0.36 LSB’s rms is displayed via
a grounded histogram and is shown in Figure 13.
FREQUENCY – MHz
AMPLITUDE – dBFigure 22.Full-Power Bandwidth
Figure 23.Settling Time
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two condi-
tions: (1) the common-mode voltage is centered around mid
supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, QS1, being CMOS
switches whose RON resistance is very low but has some signal
dependency which causes frequency dependent ac distortion
while the SHA is in the track mode. The RON resistance of a
CMOS switch is typically lowest at its midsupply but increases
symmetrically as the input signal approaches either AVDD or
AVSS. A lower input signal voltage span centered at midsupply
reduces the degree of RON modulation.
tion in THD performance as the input frequency increases.
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be domi-
nated by static nonlinearities such as INL and DNL. It is
important to note that these dc static nonlinearities are inde-
pendent of any RON modulation.
Figure 24.AD9243 THD vs. Frequency for VCM = 2.5 V and
1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. Also, the
required input signal voltage span is reduced by a half which
further reduces the degree of RON modulation and its effects on
distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the
2 V and 5V input span as specified in the AD9243 “DC
SPECIFICATIONS.”
Referring to Figure 21, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input imped-
ance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, CPIN, parasitic capacitance
CPAR, and the sampling capacitance, CS, is typically less thanpF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on CS to the new
input voltage. This action of charging and discharging CS which
is approximately 4 pF, averaged over a period of time and for a
given sampling frequency, FS, makes the input impedance ap-
pear to have a benign resistive component (i.e., 83 kΩ at FS =
3.0 MSPS). However, if this action is analyzed within a sam-
pling period (i.e., T = <1/FS), the input impedance is dynamic
due to the instantaneous requirement of charging and discharg-
ing CS. A series resistor inserted between the input drive source
and the SHA input as shown in Figure 25 provides the effective
AD9243Figure 25.Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several factors
which include the AD9243 sampling rate, the selected op amp,
and the particular application. In most applications, a 30 Ω toΩ resistor is sufficient. However, some applications may re-
quire a larger resistor value to reduce the noise bandwidth or
possibly limit the fault current in an overvoltage condition.
Other applications may require a larger resistor value as part of
an anti-aliasing filter. In any case, since the THD performance
is dependent on the series resistance and the above mentioned
factors, optimizing this resistor value for a given application is
encouraged.
A slight improvement in SNR performance and dc offset perfor-
mance is achieved by matching the input resistance connected
to VINA and VINB. The degree of improvement is dependent on
the resistor value and the sampling rate. For series resistor
values greater than 100 Ω, the use of a matching resistor is
encouraged.
The noise or small-signal bandwidth of the AD9243 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wide-
band noise at the A/D’s input by forming a low-pass filter.
Note, however, that the combination of this series resistance
with the equivalent input capacitance of the AD9243 should be
evaluated for those time-domain applications that are sensitive
to the input signal’s absolute settling time. In applications where
harmonic distortion is not a primary concern, the series resis-
tance may be selected in combination with the SHA’s nominal
16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9243, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts like a charge reservoir, sinking or sourcing the addi-
tional charge required by the hold capacitor, CH, further reduc-
ing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9243 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response, and dis-
tortion performance.
Table I.Analog Input Configuration SummarySingle-Ended
REFERENCE OPERATIONThe AD9243 contains an onboard bandgap reference that pro-
vides a pin-strappable option to generate either a 1 V or 2.5 V
output. With the addition of two external resistors, the user can
generate reference voltages other than 1 V and 2.5 V. Another
alternative is to use an external reference for designs requiring
enhanced accuracy and/or drift performance. See Table II for a
summary of the pin-strapping options for the AD9243 reference
configurations.
Figure 26 shows a simplified model of the internal voltage
reference of the AD9243. A pin-strappable reference amplifier
buffers a 1 V fixed reference. The output from the reference
amplifier, A1, appears on the VREF pin. The voltage on the
VREF pin determines the full-scale input span of the A/D. This
input span equals,
Full-Scale Input Span = 2 × VREF
CAPT
VREFREFCOM
SENSE
CAPBFigure 26.Equivalent Reference Circuit
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators which monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is con-
nected to the internal resistor network thus providing a VREF of
2.5 V. If the SENSE pin is tied to the VREF pin via a short or
resistor, the switch is connected to the SENSE pin. A short will
provide a VREF of 1.0 V while an external resistor network will
provide an alternative VREF between 1.0 V and 2.5 V. The
other comparator controls internal circuitry which will disable
the reference amplifier if the SENSE pin is tied AVDD. Dis-
abling the reference amplifier allows the VREF pin to be driven
by an external voltage reference.
The actual reference voltages used by the internal circuitry of
the AD9243 appear on the CAPT and CAPB pins. For proper
operation when using the internal or an external reference, it is
necessary to add a capacitor network to decouple these pins.
Figure 27 shows the recommended decoupling network. This
capacitive network performs the following three functions: (1)
along with the reference amplifier, A2, it provides a low source
impedance over a large frequency range to drive the A/D inter-
nal circuitry, (2) it provides the necessary compensation for A2,
and (3) it bandlimits the noise contribution from the reference.
The turn-on time of the reference voltage appearing between
CAPT and CAPB is approximately 15ms and should be evalu-
ated in any power-down mode of operation.
0.1mFFigure 27.Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4 respec-
tively in which the input span can be varied between 2V and 5V.
Note that those samples within the pipeline A/D during any
reference transition will be corrupted and should be discarded.
Table II.Reference Configuration Summary
AD9243
DRIVING THE ANALOG INPUTS
INTRODUCTIONThe AD9243 has a highly flexible input structure allowing it to
interface with single-ended or differential input interface cir-
cuitry. The applications shown in sections “Driving the Analog
Inputs” and “Reference Configurations” along with the infor-
mation presented in “Input and Reference Overview” of this
data sheet, give examples of both single-ended and differential
operation. Refer to Tables I and II for a list of the different
possible input and reference configurations and their associated
figures in the data sheet.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power supply
options. For example, a dc coupled single-ended input may be
appropriate for many data acquisition and imaging applications.
Also, many communication applications which require a dc
coupled input for proper demodulation can take advantage of
the excellent single-ended distortion performance of the AD9243.
The input span should be configured such that the system’s
performance objectives and the headroom requirements of the
driving op amp are simultaneously met.
Alternatively, the differential mode of operation provides the
best THD and SFDR performance over a wide frequency range.
A transformer coupled differential input should be considered
for the most demanding spectral-based applications which allow
ac coupling (e.g., Direct IF to Digital Conversion). The dc-
coupled differential mode of operation also provides an enhance-
ment in distortion and noise performance at higher input spans.
Furthermore, it allows the AD9243 to be configured for a 5 V
span using op amps specified for +5 V or ±5 V operation.
Single-ended operation requires that VINA be ac or dc coupled
to the input signal source while VINB of the AD9243 be biased
to the appropriate voltage corresponding to a midscale code
transition. Note that signal inversion may be easily accom-
plished by transposing VINA and VINB.
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are in and out of
phase versions of the input signal. Differential operation of the
AD9243 offers the following benefits: (1) Signal swings are
smaller and therefore linearity requirements placed on the input
signal source may be easier to achieve, (2) Signal swings are
smaller and therefore may allow the use of op amps which may
otherwise have been constrained by headroom limitations, (3)
Differential operation minimizes even-order harmonic products,
and (4) Differential operation offers noise immunity based on
the device’s common-mode rejection as shown in Figure 16.
As is typical of most CMOS devices, exceeding the supply limits
will turn on internal parasitic diodes resulting in transient cur-
rents within the device. Figure 28 shows a simple means of
clamping a dc coupled input with the addition of two series
resistors and two diodes. Note that a larger series resistor could
be used to limit the fault current through D1 and D2 but should be
evaluated since it can cause a degradation in overall performance.
Figure 28.Simple Clamping Circuit
DIFFERENTIAL MODE OF OPERATIONSince not all applications have a signal preconditioned for
differential operation, there is often a need to perform a single-
ended-to-differential conversion. A single-ended-to-differential
conversion can be realized with an RF transformer or a dual op
amp differential driver. The optimum method depends on
whether the application requires the input signal to be ac or dc
coupled to AD9243.
AC Coupling via an RF TransformerIn applications that do not need to be dc coupled, an RF trans-
former with a center tap is the best method to generate differen-
tial inputs for the AD9243. It provides all the benefits of
operating the A/D in the differential mode without contributing
additional noise or distortion. An RF transformer has the added
benefit of providing electrical isolation between the signal source
and the A/D.
Figure 29 shows the schematic of the suggested transformer
circuit. The circuit uses a Mini-Circuits RF transformer, model
#T4-6T, which has an impedance ratio of four (turns ratio of
2). The schematic assumes that the signal source has a 50 Ω
source impedance. The 1:4 impedance ratio requires the 200 Ω
secondary termination for optimum power transfer and VSWR.
The centertap of the transformer provides a convenient means
of level shifting the input signal to a desired common-mode
voltage. Optimum performance can be realized when the centertap
is tied to CML of the AD9243 which is the common-mode bias
level of the internal SHA.
Figure 29.Transformer Coupled Input
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improve-
ment in distortion performance at reduced output power levels
and signal swings. Hence, selecting a transformer with a higher
impedance ratio (i.e., Mini-Circuits T16-6T with a 1:16 imped-
ance ratio) effectively “steps up” the signal level, further reduc-
ing the driving requirements of the signal source.
