AD9240AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD9240AS ,Complete 14-Bit, 10 MSPS Monolithic A/D ConverterSPECIFICATIONS T to T unless otherwise noted)MIN MAXParameter AD9240 UnitsRESOLUTION 14 Bits minMAX ..
AD9241AS ,Complete 14-Bit, 1.25 MSPS Monolithic A/D ConverterFEATURESFUNCTIONAL BLOCK DIAGRAMMonolithic 14-Bit, 1.25 MSPS A/D ConverterLow Power Dissipation: 60 ..
AD9243AS ,Complete 14-Bit, 3.0 MSPS Monolithic A/D ConverterSPECIFICATIONS otherwise noted)Parameter AD9243 UnitsRESOLUTION 14 Bits minMAX CONVERSION RATE 3 MH ..
AD9244BST-40 ,14-Bit, 40/65 MSPS Monolithic A/D ConverterAPPLICATIONSAGND CML VR VREF REF REF DRGNDCommunications Subsystems (Microcell, Picocell)SENSE GNDM ..
AD9244BST-65 ,14-Bit, 40/65 MSPS Monolithic A/D Converterfeaturesthe DC accuracy and temperature drift requirements of thea separate digital output driver s ..
AD9244BST-65 ,14-Bit, 40/65 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, CLKVDD=3V, DRVDD = +3.0 V, f = 65 MSPS (-65) or 40MSPS (-40), INPUT RA ..
ADS7818PG4 ,12-Bit High Speed Low Power Sampling Analog-to-Digital Converter 8-PDIP -40 to 85MAXIMUM RATINGSELECTROSTATIC+V to GND .... –0.3V to 6VCCDISCHARGE SENSITIVITYAnalog Inputs to GND . ..
ADS7819P ,12-Bit 800kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7819U ,12-Bit 800kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7820U ,12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7822 ,12-Bit High Speed 2.7V Micro Power Sampling ANALOG-TO-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS: +V = +2.7VCCAt –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 75kHz, and f ..
ADS7822E/250 ,12-Bit High Speed 2.7V Micro Power Sampling Analog-To-Digital ConverterELECTRICAL CHARACTERISTICS: +V = +2.7VCCAt –40°C to +85°C, +V = +2.7V, V = +2.5V, f = 75kHz, and f ..

AD9240AS
Complete 14-Bit, 10 MSPS Monolithic A/D Converter
REV.AComplete 14-Bit, 10 MSPS
Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
VINA
CAPT
CAPB
SENSE
OTR
BIT 1
(MSB)
BIT 14
(LSB)
VREF
DVSSAVSS
VINB
REFCOM
DVDDAVDDCLK
DRVDD
DRVSS
CML
BIAS
FEATURES
Monolithic 14-Bit, 10 MSPS A/D Converter
Low Power Dissipation: 285 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio:77.5 dB
Spurious-Free Dynamic Range:90 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Lead MQFP
PRODUCT HIGHLIGHTS
The AD9240 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-lead Metric Quad
Flatpack.
Low Power and Single Supply
The AD9240 consumes only 280 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9240 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9240 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
Excellent Undersampling Performance
The full power bandwidth and dynamic range of the AD9240
make it well suited for Direct-IF Down Conversion extending to
45 MHz.
PRODUCT DESCRIPTION
The AD9240 is a 10 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9240 is highly flexible, allowing for easy
interfacing to imaging, communications, medical and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. The
AD9240 also performs well in communication systems employ-
ing Direct-IF Down Conversion, since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 5MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
AD9240–SPECIFICATIONS
DC SPECIFICATIONS
NOTESVREF = 1 V.Including internal reference.Excluding internal reference.Load regulation with 1 mA load current (in addition to that required by the AD9240).
Specification subject to change without notice.
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, fSAMPLE = 10 MSPS, RBIAS = 2kV, VREF = 2.5 V, VINB = 2.5 V,
TMIN to TMAX unless otherwise noted)
AC SPECIFICATIONS
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE RATIO (SNR)
TOTAL HARMONIC DISTORTION (THD)
SPURIOUS FREE DYNAMIC RANGE
DYNAMIC PERFORMANCE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
LOGIC OUTPUTS (with DRVDD = 5 V)
LOGIC OUTPUTS (with DRVDD = 3 V)
AD9240
(AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, fSAMPLE = 10 MSPS, RBIAS = 2kV, VREF = 2.5 V, AIN = –0.5 dBFS,
AC Coupled/Differential Input, TMIN to TMAX unless otherwise noted)
(AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)
AD9240
ABSOLUTE MAXIMUM RATINGS*
Digital Outputs
VREF
SENSE
CAPB, CAPT
BIAS
Junction Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
SWITCHING SPECIFICATIONS
NOTESThe clock period may be extended to 1 ms without degradation in specified performance @ +25°C.
Specifications subject to change without notice.
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, RBIAS = 2kV, CL = 20 pF)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Figure 1.Timing Diagram
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFPJA = 53.2°C/WJC = 19°C/W
ORDERING GUIDE
*S = Metric Quad Flatpack.
PIN CONFIGURATION
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, an effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDR
The ratio of the rms value of either input tone to the rms value
PIN FUNCTION DESCRIPTIONS
*See Speed/Power Programmability section.
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
AD9240
Typical Differential AC Characterization Curves/Plots
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5V, fSAMPLE =MSPS, RBIAS = 2kV, TA = +258C, Differential Input)
INPUT FREQUENCY – MHz
SINAD – dB
Figure 2.SINAD vs. Input Frequency
(Input Span = 5 V, VCM = 2.5 V)
INPUT FREQUENCY – MHz
SINAD – dB
Figure 5.SINAD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
SAMPLE RATE – MHz
THD – dB
Figure 8.THD vs. Sample Rate
(fIN = 5.0MHz, AIN = –0.5dBFS,
VCM = 2.5 V)
INPUT FREQUENCY – MHz
THD – dB
Figure 3.THD vs. Input Frequency
(Input Span = 5V, VCM = 2.5 V)
INPUT FREQUENCY – MHz
THD – dB
Figure 6.THD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
AIN – dB
SFDR – dBc AND dBFS
100
Figure 9.Single Tone SFDR
(fIN = 5.0MHz, VCM = 2.5 V)
FREQUENCY – MHz
AMPLITUDE – dB
–120
Figure 4.Typical FFT, fIN = 1.0MHz
(Input Span = 5V, VCM = 2.5 V)
FREQUENCY – MHz
AMPLITUDE – dB
–1505.0
Figure 7.Typical FFT, fIN = 5.0MHz
(Input Span = 2V, VCM = 2.5 V)
INPUT POWER LEVEL (f1 = f2) – dBFS
WORST CASE SPURIOUS – dBc AND dBFS
100
Figure 10.Dual Tone SFDR
(f1 = 0.95 MHz, f2 = 1.04 MHz,
VCM = 2.5 V)
Other Characterization Curves/Plots
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5V, fSAMPLE = 10 MSPS, RBIAS = 2kV,
TA = +258C, Single-Ended Input)
CODE
INL – LSB
–3.0
Figure 11.Typical INL
(Input Span = 5 V)
INPUT FREQUENCY – MHz0.112010
SINAD – dB
Figure 14.SINAD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
INPUT FREQUENCY – MHz
SINAD – dB
Figure 17.SINAD vs. Input Frequency
(Input Span = 5 V, VCM = 2.5 V)
CODE
DNL – LSB
0.0
Figure 12.Typical DNL
(Input Span = 5 V)
INPUT FREQUENCY – MHz
THD – dB
Figure 15.THD vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
INPUT FREQUENCY – MHz
THD – dB
Figure 18.THD vs. Input Frequency
(Input Span = 5 V, VCM = 2.5 V)
Figure 13.“Grounded-Input”
Histogram (Input Span = 5 V)
FREQUENCY – MHz
AMPLITUDE – dB
Figure 16.CMR vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V)
Figure 19.Typical Voltage Reference
Error vs. Temperature
AD9240
CLOCK FREQUENCY – MHz
SINAD – dB
12010
Figure 21.SINAD vs. Clock Frequency for Varying RBIAS
Values (VCM = 2.5V, AIN = –0.5dB, 5V Span, fIN = fCLK/2)
CLOCK FREQUENCY – MHz
POWER – mW
150
Figure 22.Power Dissipation vs. Clock Frequency for
Varying RBIAS Values
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 23, a simplified model of the AD9240, highlights the rela-
tionship between the analog inputs, VINA, VINB, and the ref-
erence voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D core. The minimum input
voltage to the A/D core is automatically defined to be –VREF.
Figure 23.Equivalent Functional Input Circuit
INTRODUCTION
The AD9240 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D con-
nected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ-
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er-
rors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
The AD9240 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
Speed/Power Programmability
The AD9240’s maximum conversion rate and associated power
dissipation can be set using the part’s BIAS pin. A simplified
diagram of the on-chip circuitry associated with the BIAS pin is
shown in Figure 20.
Figure 20.
The value of RBIAS can be varied over a limited range to set the
maximum sample rate and power dissipation of the AD9240. A
typical plot of S/(N+D) @ fIN = Nyquist vs. fCLK at varying
RBIAS is shown in Figure 21. A similar plot of power vs. fCLK
at varying RBIAS is shown in Figure 22. These plots indicate
typical performance vs. RBIAS. Note that all other plots and
specifications in this data sheet reflect performance at a fixed
RBIAS = 2kW.
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily con-
figure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
VCORE = VINA – VINB(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF £ VCORE £ VREF
(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9240. The
power supplies bound the valid operating range for VINA and
VINB. The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V
(3)
AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9240, see
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations.
ANALOG INPUT OPERATION
Figure 24 shows the equivalent analog input of the AD9240
which consists of a differential sample-and-hold amplifier (SHA).
The differential input structure of the SHA is highly flexible,
allowing the devices to be easily configured for either a differen-
tial or single-ended input. The dc offset, or common-mode
voltage, of the input(s) can be set to accommodate either single-
supply or dual supply systems. Note also that the analog inputs,
VINA and VINB, are interchangeable with the exception that
reversing the inputs to the VINA and VINB pins results in a
polarity inversion.
The input SHA of the AD9240 is optimized to meet the perfor-
mance requirements for some of the most demanding commu-
nication, imaging, and data acquisition applications while
maintaining low power dissipation. Figure 25 is a graph of the
full-power bandwidth of the AD9240, typically 60 MHz. Note
that the small signal bandwidth is the same as the full-power
bandwidth. The settling time response to a full-scale stepped
input is shown in Figure 26 and is typically less than 40 ns to
0.0025%. The low input referred noise of 0.36 LSB’s rms is
displayed via a grounded histogram and is shown in Figure 13.
FREQUENCY – MHz10100
AMPLITUDE – dB
Figure 25.Full-Power Bandwidth
Figure 26.Settling Time
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two condi-
tions: (1) the common-mode voltage is centered around mid-
supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, QS1, being CMOS
switches whose RON resistance is very low but has some signal
dependency which causes frequency dependent ac distortion
while the SHA is in the track mode. The RON resistance of a
CMOS switch is typically lowest at its midsupply but increases
symmetrically as the input signal approaches either AVDD or
AVSS. A lower input signal voltage span centered at midsupply
reduces the degree of RON modulation.
AD9240
Figure 27 compares the AD9240’s THD vs. frequency perfor-
mance for a 2 V input span with a common-mode voltage ofV and 2.5 V. Note the difference in the amount of degrada-
tion in THD performance as the input frequency increases.
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be domi-
nated by static nonlinearities such as INL and DNL. It is
important to note that these dc static nonlinearities are inde-
pendent of any RON modulation.
THD – dB
FREQUENCY – MHz
Figure 27.THD vs. Frequency for VCM = 2.5 V and1.0 V
(AIN = –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. Also, the
required input signal voltage span is reduced a factor of two
which further reduces the degree of RON modulation and its
effects on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the
2 V and 5V input span as specified in the AD9240 DC
SPECIFICATIONS.
Referring to Figure 24, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input imped-
ance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, CPIN, parasitic capacitance
CPAR, and the sampling capacitance, CS, is typically less thanpF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on CS to the new
input voltage. This action of charging and discharging CS which
is approximately 4 pF, averaged over a period of time and for a
given sampling frequency, FS, makes the input impedance ap-
pear to have a benign resistive component (i.e., 83 kW at FS =
10 MSPS). However, if this action is analyzed within a sam-
pling period (i.e., T = <1/FS), the input impedance is dynamic
Figure 28.Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several fac-
tors, which include the AD9240 sampling rate, the selected op
amp and the particular application. In most applications, a
30 W to 50W resistor is sufficient; however, some applications
may require a larger resistor value to reduce the noise band-
width or possibly limit the fault current in an overvoltage
condition. Other applications may require a larger resistor value
as part of an antialiasing filter. In any case, since the THD
performance is dependent on the series resistance and the above
mentioned factors, optimizing this resistor value for a given
application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance con-
nected to VINA and VINB. The degree of improvement is de-
pendent on the resistor value and the sampling rate. For series
resistor values greater than 100 W, the use of a matching resis-
tor is encouraged.
The noise or small-signal bandwidth of the AD9240 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wide-
band noise at the A/D’s input by forming a low-pass filter. Note,
however, that the combination of this series resistance with the
equivalent input capacitance of the AD9240 should be evalu-
ated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where har-
monic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF
of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9240, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts as a charge reservoir, sinking or sourcing the additional
charge required by the hold capacitor, CH, further reducing
current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9240 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
Table I.Analog Input Configuration Summary
DifferentialVINA and VINB can be interchanged if signal inversion is required.
Table II.Reference Configuration Summary
EXTERNAL
AD9240
REFERENCE OPERATION
The AD9240 contains an onboard bandgap reference that pro-
vides a pin-strappable option to generate either a 1 V or 2.5 V
output. With the addition of two external resistors, the user can
generate reference voltages other than 1 V and 2.5 V. Another
alternative is to use an external reference for designs requiring
enhanced accuracy and/or drift performance. See Table II for a
summary of the pin-strapping options for the AD9240 reference
configurations.
Figure 29 shows a simplified model of the internal voltage
reference of the AD9240. A pin-strappable reference ampli-
fier buffers a 1 V fixed reference. The output from the refer-
ence amplifier, A1, appears on the VREF pin. The voltage on
the VREF pin determines the full-scale input span of the A/D.
This input span equals,
Full-Scale Input Span = 2 · VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators which monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is con-
nected to the internal resistor network thus providing a VREF of
2.5 V. If the SENSE pin is tied to the VREF pin via a short or
resistor, the switch is connected to the SENSE pin. A short will
provide a VREF of 1.0 V while an external resistor network will
provide an alternative VREF between 1.0 V and 2.5 V.
The second comparator controls internal circuitry that will
disable the reference amplifier if the SENSE pin is tied AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
CAPT
CAPB
VREF
SENSE
REFCOM
Figure 29.Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9240 appear on the CAPT and CAPB pins. For proper
operation when using the internal or an external reference, it is
necessary to add a capacitor network to decouple these pins.
Figure 30 shows the recommended decoupling network. This
capacitive network performs the following three functions: (1)
along with the reference amplifier, A2, it provides a low source
impedance over a large frequency range to drive the A/D inter-
nal circuitry, (2) it provides the necessary compensation for A2
and (3) it bandlimits the noise contribution from the reference.
The turn-on time of the reference voltage appearing between
CAPT and CAPB is approximately 15ms and should be evalu-
ated in any power-down mode of operation.
Figure 30.Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec-
tively, where the input span can be varied between 2V and 5V.
Note that those samples within the pipeline A/D during any
reference transition will be corrupted and should be discarded.

Partno	Mfg	Dc	Qty	Available	Descript
AD9240AS	ADI	N/a	7027	avai	Complete 14-Bit, 10 MSPS Monolithic A/D Converter