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AD9238BST-65-AD9238BSTRL-20
12-Bit, 20/40/65 MSPS Dual A/D Converter
12-Bit, 20/40/65 MSPS
Dual A/D Converter
FUNCTIONAL BLOCK DIAGRAM
OEB_A
OTR_A
D11_A
D0_A
MUX_SELECT
CLK_A
CLK_B
DCS
DFS
PDWN_A
PDWN_B
SHARED_REF
OEB_B
OTR_B
D11_B
D0_B
DRGNDAGND
DRVDDAVDD
VIN+_A
VIN–_A
REFT_A
REFB_A
VREF
SENSE
AGND
REFB_B
REFT_B
VIN–_B
VIN+_B
FEATURES
Integrated Dual 12-Bit Analog-to-Digital Converters
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 70 dBc (to Nyquist, AD9238-65)
SFDR = 85 dBc (to Nyquist, AD9238-65)
Low Power: 600 mW at 65 MSPS
Differential Input with 500 MHz 3 dB Bandwidth
On-Chip Reference and SHA
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
PRODUCT HIGHLIGHTS1. Integrated, dual version of the AD9235—a 12-bit,
20 MSPS/40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow fl exibility between power, cost, and performance to suit
an application.
3. The AD9238 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
4. Low power consumption:
AD9238-20 operating at 20 MSPS consumes a low 180 mW.
AD9238-40 operating at 40 MSPS consumes a low 330 mW.
AD9238-65 operating at 65 MSPS consumes a low 600 mW.
5. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be confi gured for
single-ended or differential operation.
6. Typical channel isolation of 80 dB @ fIN = 10 MHz.
7. The clock duty cycle stabilizer (AD9238-65 only) maintains
performance over a wide range of clock duty cycles.
8. The OTR output bits indicate when either input signal is
beyond the selected input range.
9. Multiplexed data output option enables single-port operation
from either data port A or data port B.
GENERAL DESCRIPTIONThe AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter. It features dual high performance
sample-and-hold amplifi ers and an integrated voltage reference.
The AD9238 uses a multistage differential pipelined architecture
with output error correction logic to provide 12-bit accuracy and
guarantee no missing codes over the full operating temperature
range at data rates up to 65 MSPS.
The wide bandwidth, differential SHA allows for a variety of
user selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including multi-
plexed systems that switch full-scale voltage levels in successive
channels and for sampling inputs at frequencies well beyond the
Nyquist rate. The AD9238 is suitable for applications in commu-
nications, imaging, and medical ultrasound.
Dual single-ended clock inputs are used to control all internal con-
version cycles. A duty cycle stabilizer is available on the AD9238-65
and can compensate for wide variations in the clock duty cycle,
allowing the converters to maintain excellent performance. The
digital output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overfl ow
condition, which can be used with the most signifi cant bit to deter-
mine low or high overfl ow.
Fabricated on an advanced CMOS process, the AD9238 is avail-
able in a space saving 64-lead LQFP and is specifi ed over the
industrial temperature range (–40°C to +85°C).
REV. A
AD9238–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input,
1.0 V Internal Reference, TMIN to TMAX, un less oth er wise noted.)DC SPECIFICATIONS REFERENCE INPUT RESISTANCE
POWER SUPPLIES
AVDD
DRVDD
IAVDD
IDRVDD
NOTESGain error and gain temperature coeffi cient are based on the A/D converter only (with a fi xed 1.0 V external reference).Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 2 for the equivalent analog input structure.Measured with dc input at maximum clock rate.Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifi cations subject to change without notice.
