AD9224ARS ,Complete 12-Bit 40 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 40 MSPS A/D ConverterAVDD DRVDDCLKLow Power Dissipation: 415 mWSHASingle ..
AD9225AR ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 25 MSPS A/D ConverterCLK AVDD DRVDDLow Power Dissipation: 280 mWSingle + ..
AD9225ARS ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, DRVDD = +5 V, f = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T to T unles ..
AD9226 ,12-Bit, 65 MSPS Analog-to-Digital ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMSignal-to-Noise Ratio: 69 dB @ f = 31 MHzINDRVDDCLK AVDDSpurious-F ..
AD9226ARS ,Complete 12-Bit, 65 MSPS ADC ConverterSPECIFICATIONS noted.)Parameter Temp Test Level Min Typ Max UnitRESOLUTION 12 BitsACCURACYIntegral ..
AD9226ARS ,Complete 12-Bit, 65 MSPS ADC ConverterSPECIFICATIONS SAMPLE MIN MAXParameters Temp Test Level Min Typ Max Unit1 1 LOGIC INPUTS (Clock, DF ..
ADS7807UB ,Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTERPIN DESCRIPTIONSDIGITALPIN # NAME I/O DESCRIPTION1R1 Analog Input. See Figure 7.IN2 AGND1 Analog Se ..
ADS7808P ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERADS7808SBAS018A – JANUARY 1992 – REVISED SEPTEMBER 200312-Bit 10µ s Serial CMOS SamplingANALOG-to-D ..
ADS7808P ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATICAnalog Inputs: R1 .. ±25VINR2 .. ±25VDISCHARGE SENSITIVITYINR3 .. ±25VI ..
ADS7808U ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERELECTRICAL CHARACTERISTICSAt T = –40°C to +85°C, f = 100kHz, V = V = +5V, using internal reference ..
ADS7808U ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERPIN ASSIGNMENTSPIN # NAME DESCRIPTION1R1 Analog Input. See Table I and Figure 4 for input range con ..
ADS7808U/1KE4 ,12-Bit 10us Serial CMOS Sampling Analog-to-Digital Converter 20-SOIC -40 to 85FEATURES DESCRIPTION* 100kHz SAMPLING RATE The ADS7808 is a complete 12-bit sampling analog-to-digi ..
AD9224ARS
Complete 12-Bit 40 MSPS Monolithic A/D Converter
REV.A
Complete 12-Bit, 40 MSPS
Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
VINA
CAPT
CAPB
SENSE
OTR
BIT 1
(MSB)
BIT 12
(LSB)
VREF
DRVSSAVSS
VINB
REFCOM
DRVDDAVDDCLKCML
FEATURES
Monolithic 12-Bit, 40 MSPS A/D Converter
Low Power Dissipation: 415 mW
Single +5 V Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: 60.33 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 68.3 dB
Spurious-Free Dynamic Range: 81 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SSOP Package
Compatible with 3 V Logic
PRODUCT DESCRIPTIONThe AD9224 is a monolithic, single supply, 12-bit, 40 MSPS,
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier and voltage reference. The AD9224
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 40 MSPS
data rates, and guarantees no missing codes over the full operat-
ing temperature range.
The AD9224 combines a low cost high speed CMOS process
and a novel architecture to achieve the resolution and speed of
existing bipolar implementations at a fraction of the power
consumption and cost.
The input of the AD9224 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets, including single-ended applications. The dynamic per-
formance is excellent.
The sample-and-hold (SHA) amplifier is well suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and well beyond the Nyquist rate.
The AD9224’s wideband input, combined with the power and
cost savings over previously available monolithics, is suitable for
applications in communications, imaging and medical ultrasound.
The AD9224 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal indicates an overflow
condition which can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTSThe AD9224 is fabricated on a very cost effective CMOS
process. High speed precision analog circuits are now combined
with high density logic circuits.
The AD9224 offers a complete single-chip sampling 12-bit,
40 MSPS analog-to-digital conversion function in 28-lead
SSOP package.
Low Power—The AD9224 at 415 mW consumes a fraction ofthe power of presently available in existing monolithic solutions.
On-Board Sample-and-Hold (SHA)—The versatile SHAinput can be configured for either single-ended or differential
inputs.
Out of Range (OTR)—The OTR output bit indicates whenthe input signal is beyond the AD9224’s input range.
Single Supply—The AD9224 uses a single +5 V power supplysimplifying system power supply design. It also features a sepa-
rate digital driver supply line to accommodate 3 V and 5 V logic
families.
Pin Compatibility—The AD9224 is pin compatible with theAD9220, AD9221, AD9223 and AD9225 ADCs.
AD9224–SPECIFICATIONSNOTESIncludes internal voltage reference error.Excludes internal voltage reference error.Load regulation with 1 mA load current (in addition to that required by the AD9224).
Specifications subject to change without notice.
(AVDD = +5 V, DRVDD = +3 V, fSAMPLE = 40 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, TMIN to TMAX unless otherwise noted)DC SPECIFICATIONS
AD9224AC SPECIFICATIONSSpecifications subject to change without notice.
DIGITAL SPECIFICATIONSSpecifications subject to change without notice.
SWITCHING SPECIFICATIONSNOTES
1The clock period may be extended to 1 ms without degradation in specified performance @ +25°C.For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text.
Specifications subject to change without notice.
(AVDD = +5 V, DRVDD = +3 V, fSAMPLE = 40 MSPS, VREF= 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted)
(AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)
(TMIN to TMAX with AVDD = + 5 V, DRVDD = +5 V, CL = 20 pF)
AD9224
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9224 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Figure 1.Timing Diagram
PIN CONFIGURATION
28-Lead SSOP
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
ZERO ERRORThe major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERRORThe first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
TEMPERATURE DRIFTThe temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTIONThe specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
APERTURE JITTERAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAYAperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIOS/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
AD9224
Typical Performance Characteristics(AVDD, DVDD = +5 V, FS = 40 MHz [50% duty cycle] unless otherwise noted.)
Title
DNL – LSB
CODEFigure 2.␣Typical DNL
INPUT FREQUENCY – MHz
SINAD – dB65605550454035302520151050.5Figure 3.SINAD vs. Input Frequency (Input Span =
4.0 V p-p, VCM = 2.5 V Differential Input)
INL – LSB
CODEFigure 5.Typical INL
INPUT FREQUENCY – MHz
SINAD – dB
0.510203040705060Figure 6.SINAD vs. Input Frequency (Input Span =
2.0 V p-p, VCM = 2.5 V Differential Input)
Figure 8.SNR/SFDR vs. AIN (Input Amplitude) (fIN = 20 MHz,
Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input)
20151050.5
INPUT FREQUENCY
+SNR/–THDFigure 9.+SNR/–THD vs. Input Frequency (Input Span =
4.0 V p-p, VCM = 2.5 V Single-Ended Input)
Figure 10.␣“Grounded-Input” Histogram (Input Span =
2 V p-p)
Figure 11.THD vs. Sample Rate (AIN = –0.5 dB, VCM = 2.5 V
Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input)
Figure 12.+SNR/–THD vs. Input Frequency (FS = 32 MHz,
Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input)
AD9224
INTRODUCTIONThe AD9224 is a high performance, complete single-supply 12-
bit ADC. The analog input range of the AD9224 is highly flex-
ible allowing for both single-ended or differential inputs of
varying amplitudes that can be ac or dc coupled.
It utilizes a four-stage pipeline architecture with a wideband
input sample-and-hold amplifier (SHA) implemented on a cost-
effective CMOS process. Each stage of the pipeline, excluding
the last stage, consists of a low resolution flash A/D connected
to a switched capacitor DAC and interstage residue amplifier
(MDAC). The residue amplifier amplifies the difference be-
tween the reconstructed DAC output and the flash input for the
next stage in the pipeline. One bit of redundancy is used in each
of the stages to facilitate digital correction of flash errors. The
last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers of the
AD9224 can be configured to interface with +5 V or +3.3 V
logic families.
The AD9224 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in hold. Sys-
tem disturbances just prior to the rising edge of the clock and/or
excessive clock jitter may cause the input SHA to acquire the
wrong value, and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEWFigure 13 is a simplified model of the AD9224. It highlights the
relationship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF
defines the maximum input voltage to the A/D core. The mini-
mum input voltage to the A/D core is automatically defined to
be –VREF.
Figure 13.Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
VCORE = VINA – VINB(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF £ VCORE £ VREF(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9224. The power
supplies bound the valid operating range for VINA and VINB.
The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V(3)AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. The range of valid inputs for VINA
and VINB is any combination that satisfies both Equations 2
and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9224, see
Table IV.
Refer to Table I and Table II at the end of this section for a
summary of both the various analog input and reference
configurations.
ANALOG INPUT OPERATIONFigure 14 shows the equivalent analog input of the AD9224
which consists of a differential sample-and-hold amplifier
(SHA). The differential input structure of the SHA is highly
flexible, allowing the devices to be easily configured for either a
differential or single-ended input. The dc offset, or common-
mode voltage, of the input(s) can be set to accommodate either
single-supply or dual-supply systems. Note also, that the analog
inputs, VINA and VINB, are interchangeable, with the excep-
tion that reversing the inputs to the VINA and VINB pins re-
sults in a polarity inversion.
Figure 14.Simplified Input Circuit
The AD9224 has a wide input range. The input peaks may be
moved to AVDD or AVSS before performance is compromised.
This allows for much greater flexibility when selecting single-
ended drive schemes. Op amps and ac coupling clamps can be
Due to the high degree of symmetry within the SHA topology,
a significant improvement in distortion performance for differ-
ential input signals with frequencies up to and beyond Nyquist
can be realized. This inherent symmetry provides excellent
cancellation of both common-mode distortion and noise.
Also, the required input signal voltage span is reduced by a
half which further reduces the degree of RON modulation and
its effects on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 4 V input span) and matched
input impedance for VINA and VINB. Only a slight degrada-
tion in dc linearity performance exists between the 2 V and
4 V input spans.
Referring to Figure 14, the differential SHA is implemented
using a switched-capacitor topology. Its input impedance and
its switching effects on the input drive source should be consid-
ered in order to maximize the converter’s performance. The
combination of the pin capacitance, CPIN, parasitic capacitance
CPAR, and the sampling capacitance, CS, is typically less than
5 pF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on CS to the new
input voltage. This action of charging and discharging CS,
averaged over a period of time and for a given sampling fre-
quency, FS, makes the input impedance appear to have a be-
nign resistive component. However, if this action is analyzed
within a sampling period (i.e., T = 1/FS), the input impedance
is dynamic and hence certain precautions on the input drive
source should be observed.
The resistive component to the input impedance can be com-
puted by calculating the average charge drawn by CH from the
input drive source. It can be shown that if CS is allowed to
fully charge up to the input voltage before switches QS1 are
opened, the average current into the input is the same as if
there were a resistor of 1/(CS FS) ohms connected between the
inputs. This means that the input impedance is inversely pro-
portional to the converter’s sample rate. Since CS is only 5 pF,
this resistive component is typically much larger than that of
the drive source (i.e., 5 kW at FS = 40 MSPS).
The SHA’s input impedance over a sampling period appears as
a dynamic input impedance to the input drive source. When the
SHA goes into the track mode, the input source should ideally
provide the charging current through RON of switch QS1 in an
exponential manner. The requirement of exponential charging
means that the most common input source, an op amp, must
exhibit a source impedance that is both low and resistive up to
and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a
series inductor and resistor. When a capacitive load is switched
onto the output of the op amp, the output will momentarily
drop due to its effective output impedance. As the output re-
covers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA
input as shown in Figure 15. The series resistance helps isolate
the op amp from the switched-capacitor load.
Figure 15.Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several fac-
tors, including the ADC sampling rate, the selected op amp,
and the particular application. In most applications, a 30 W to
100 W resistor is sufficient. However, some applications may
require a larger resistor value to reduce the noise bandwidth or
possibly limit the fault current in an overvoltage condition.
Other applications may require a larger resistor value as part of
an antialiasing filter. In any case, since the THD performance is
dependent on the series resistance and the above mentioned
factors, optimizing this resistor value for a given application is
encouraged.
The source impedance driving VINA and VINB should be
matched. Failure to provide that matching will result in the
degradation of the AD9224’s SNR, THD and SFDR.
For noise sensitive applications, the very high bandwidth of the
AD9224 may be detrimental and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
A/D’s input by forming a low-pass filter. Note, however, that
the combination of this series resistance with the equivalent
input capacitance of the AD9224 should be evaluated for those
time domain applications that are sensitive to the input signal’s
absolute settling time. In applications where harmonic distor-
tion is not a primary concern, the series resistance may be
selected in combination with the nominal 10 pF of input
capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9224, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts like a charge reservoir, sinking or sourcing the addi-
tional charge required by the hold capacitor, CH, further reduc-
ing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9224 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response and distor-
tion performance.
AD9224
REFERENCE OPERATIONThe AD9224 contains an onboard bandgap reference that
provides a pin strappable option to generate either a 1 V or 2 V
output. With the addition of two external resistors, the user can
generate reference voltages other than 1 V and 2 V. Another
alternative is to use an external reference for designs requiring
enhanced accuracy and/or drift performance. See Table II for a
summary of the pin-strapping options for the AD9224 refer-
ence configurations.
Figure 16 shows a simplified model of the internal voltage
reference of the AD9224. A pin strappable reference ampli-
fier buffers a 1 V fixed reference. The output from the refer-
ence amplifier, A1, appears on the VREF pin. The voltage on
the VREF pin determines the full-scale input span of the A/D.
This input span equals,
Full-Scale Input Span = 2 · VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the
voltage appearing at the SENSE pin. The logic circuitry con-
tains two comparators which monitor the voltage at the SENSE
pin. The comparator with the lowest set point (approximately
0.3 V) controls the position of the switch within the feedback
path of A1. If the SENSE pin is tied to AVSS (AGND), the
switch is connected to the internal resistor network thus provid-
ing a VREF of 2.0 V. If the SENSE pin is tied to the VREF pin
via a short or resistor, the switch will connect to the SENSE
pin. This short will provide a VREF of 1.0 V. An external resis-
tor network will provide an alternative VREF between 1.0 V
and 2.0 V. The other comparator controls internal circuitry
that will disable the reference amplifier if the SENSE pin is tied
AVDD. Disabling the reference amplifier allows the VREF pin
to be driven by an external voltage reference.
Figure 16. Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9224 appear on the CAPT and CAPB pins. For proper
operation when using the internal or an external reference, it is
necessary to add a capacitor network to decouple these pins.
Figure 17 shows the recommended decoupling network. This
capacitive network performs the following three functions: (1)
along with the reference amplifier, A2, it provides a low source
impedance over a large frequency range to drive the A/D inter-
nal circuitry, (2) it provides the necessary compensation for A2,
and (3) it bandlimits the noise contribution from the reference.
The turn-on time of the reference voltage appearing between
CAPT and CAPB is approximately 15 ms and should be evalu-
ated in any power-down mode of operation.
Figure 17. Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD,
connecting VREF to AVSS and removing the capacitive decou-
pling network. The external voltages applied to CAPT and
CAPB must be 2.0 V + Input Span/4 and 2.0 V – Input Span/4
respectively in which the input span can be varied between 2 V
and 4 V. Note that those samples within the pipeline A/D dur-
ing any reference transition will be corrupted and should be
discarded.
Table I.Analog Input Configuration SummarySingle-Ended
Differential
(via Transformer)
NOTE
1VINA and VINB can be interchanged if signal inversion is required.
Table II.Reference Configuration Summary
AD9224
DRIVING THE ANALOG INPUTSThe AD9224 has a highly flexible input structure allowing it to
interface with single-ended or differential input interface cir-
cuitry. The applications shown in Driving the Analog Inputs and
Reference Configurations sections, along with the information
presented in Input and Reference Overview of this data sheet,
give examples of both single-ended and differential operation.
Refer to Tables I and II for a list of the different possible input
and reference configurations and their associated figures in the
data sheet.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power supply
options. For example, a dc-coupled single-ended input would be
appropriate for most data acquisition and imaging applications.
Also, many communication applications that require a dc coupled
input for proper demodulation can take advantage of the
single-ended distortion performance of the AD9224. The input
span should be configured so the system’s performance objec-
tives and the headroom requirements of the driving op amp are
simultaneously met.
Differential modes of operation (ac or dc coupled input) provide
the best THD and SFDR performance over a wide frequency
range. Differential operation should be considered for the most de-
manding spectral based applications (e.g., direct IF-to-digital con-
version). See Figures 23, 24 and section on Differential Mode of
Operation. Differential input characterization was performed for
this data sheet using the configuration shown in Figure 24.
Single-ended operation requires that VINA be ac or dc coupled
to the input signal source, while VINB of the AD9224 be biased
to the appropriate voltage corresponding to a midscale code transi-
tion. Note that signal inversion may be easily accomplished by
transposing VINA and VINB. Most of the single-ended specifi-
cations for the AD9224 were characterized using Figure 21
circuitry with input spans of 4 V and 2 V as well as VCM = 2.5 V.
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are in and out of
phase versions of the input signal. Differential operation of the
AD9224 offers the following benefits: (1) Signal swings are
smaller and therefore linearity requirements placed on the input
signal source may be easier to achieve, (2) Signal swings are
smaller and therefore may allow the use of op amps which may
otherwise have been constrained by headroom limitations, (3)
Differential operation minimizes even-order harmonic products,
and (4) Differential operation offers noise immunity based on
the device’s common-mode rejection.
As is typical of most IC devices, exceeding the supply limits will
turn on internal parasitic diodes resulting in transient currents
within the device. Figure 18 shows a simple means of clamping
an ac or dc coupled single-ended input with the addition of two
series resistors and two diodes. An optional capacitor is shown
for ac coupled applications. Note that a larger series resistor
could be used to limit the fault current through D1 and D2 but
should be evaluated since it can cause a degradation in overall
performance. A similar clamping circuit could also be used for
each input if a differential input signal is being applied. The
Figure 18. Simple Clamping Circuit
SINGLE-ENDED MODE OF OPERATIONThe AD9224 can be configured for single-ended operation
using dc or ac coupling. In either case, the input of the A/D
must be driven from an operational amplifier that will not de-
grade the A/D’s performance. Because the A/D operates from a
single supply, it will be necessary to level shift ground-based
bipolar signals to comply with its input requirements. Both dc
and ac coupling provide this necessary function, but each method
results in different interface issues which may influence the
system design and performance.
Single-ended operation is often limited by the availability driv-
ing op amps. Very low distortion op amps that provide great
performance out to the Nyquist frequency of the converter are
hard to find. Compounding the problem, for dc coupled single-
ended applications, is the inability of the many high perfor-
mance amplifiers to maintain low distortions as their outputs
approach their positive output voltage limit (i.e., 1 dB compres-
sion point). For this reason, it is recommended that applications
requiring high performance dc coupling use the single-ended-to-
differential circuit shown in Figure 23.
DC COUPLING AND INTERFACE ISSUESMany applications require the analog input signal to be dc coupled
to the AD9224. An operational amplifier can be configured to
rescale and level shift the input signal so that it is compatible
with the selected input range of the A/D. The input range to the
A/D should be selected on the basis of system performance
objectives as well as the analog power supply availability since
this will place certain constraints on the op amp selection.
Many of the new high performance op amps are specified for
only –5 V operation and have limited input/output swing capa-
bilities. The selected input range of the AD9224 should be consid-
ered with the headroom requirements of the particular op amp to
prevent clipping of the signal. Also, since the output of a dual
supply amplifier can swing below absolute minimum (–0.3 V),
clamping its output should be considered in some applications.
In some applications, it may be advantageous to use an op amp
specified for single supply +5 V operation since it will inherently
limit its output swing to within the power supply rails. Ampli-
fiers like the AD8041 and AD8011 are useful for this purpose
but their low bandwidths will limit the AD9224’s performance.
High performance amplifiers (–5 V) such as the AD9631,
AD9632, AD8056 or AD8055 allow the AD9224 to be config-
ured for larger input spans which will improve the ADC’s noise
performance.
Op amp circuits using a noninverting and inverting topologies
are discussed in the next section. Although not shown, the non-
