AD9220AR-AD9220ARS-AD9221AR-AD9223AR-AD9223ARS Fast Delivery |IC PHOENIX CO.,LIMITED

AD9220AR ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSpecifications subject to change without notice.DIGITAL
AD9220ARS ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, T to T unless otherwise noted) MIN MAXParameters Symbol ..
AD9221AR ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS otherwise noted)Parameter AD9221 AD9223 AD9220 UnitsRESOLUTION 12 12 12 Bits minMAX ..
AD9222BCPZ-50 , Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter
AD9223 ,12-Bit, 1.5/3.0/10 MSPS A/D ConvertersGENERAL DESCRIPTION and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220The AD9221, AD9223, ..
AD9223AR ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS(AVDD = +5 V, DVDD = +5 V, f = Max Conversion Rate, V = 2.5 V, VINB = 2.5 V, T to T u ..
ADS7804U ,12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTERPIN CONFIGURATIONV 1 28 VIN DIG2 27AGND1 VANA3 26REF BUSYCAP 4 25 CSAGND2 5 24 R/CD11 (MSB) 6 23 BY ..
ADS7804UB ,12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATICAnalog Inputs: V ..... ±25VINDISCHARGE SENSITIVITYCAP ........ +V +0.3V ..
ADS7805U ,16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTERPIN CONFIGURATIONV 1 28 VIN DIGAGND1 2 27 VANAREF 3 26 BUSYCAP 4 25 CSAGND2 5 24 R/CD15 (MSB) 6 23 ..
ADS7805UB ,16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS (Cont.)T = –25°C to +85°C, f = 100kHz, V = V = +5V, using internal refer ..
ADS7806P ,Brown Corporation - Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7806U ,Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTERELECTRICAL CHARACTERISTICS (Cont.)At T = –40°C to +85°C, f = 40kHz, V = V = +5V, and using internal ..

AD9220AR-AD9220ARS-AD9221AR-AD9223AR-AD9223ARS
Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
REV.DComplete 12-Bit 1.5/3.0/10.0 MSPS
Monolithic A/D Converters
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are:AD9221, AD9223, and AD9220
Flexible Sampling Rates:1.5 MSPS, 3.0 MSPS and
10.0 MSPS
Low Power Dissipation: 59 mW, 100 mW and 250 mW
Single +5 V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio:70 dB
Spurious-Free Dynamic Range:86 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
suited for communication systems employing Direct-IF Down
Conversion since the SHA in the differential input mode can
achieve excellent dynamic performance far beyond its specified
Nyquist frequency.2
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9221/AD9223/AD9220 family offers a complete single-
chip sampling 12-bit, analog-to-digital conversion function in
pin-compatible 28-lead SOIC and SSOP packages.
Flexible Sampling Rates—The AD9221, AD9223 and AD9220
offer sampling rates of 1.5 MSPS, 3.0 MSPS and 10.0 MSPS,
respectively.
Low Power and Single Supply—The AD9221, AD9223 and
AD9220 consume only 59 mW, 100 mW and 250 mW, respec-
tively, on a single +5 V power supply.
Excellent DC Performance Over Temperature—The AD9221/
AD9223/AD9220 provide 12-bit linearity and temperature drift
performance.1
Excellent AC Performance and Low Noise—The AD9221/
AD9223/AD9220 provides better than 11.3 ENOB performance
and has an input referred noise of 0.09 LSB rms.2
Flexible Analog Input Range—The versatile onboard sample-
and-hold (SHA) can be configured for either single ended or differ-
ential inputs of varying input spans.
NOTESExcluding internal voltage reference.Depends on the analog input configuration.
PRODUCT DESCRIPTION
The AD9221, AD9223, and AD9220 are a generation of high
performance, single supply 12-bit analog-to-digital converters.
Each device exhibits true 12-bit linearity and temperature drift
performance1 as well as 11.5 bit or better ac performance.2 The
AD9221/AD9223/AD9220 share the same interface options,
package, and pinout. Thus, the product family provides an
upward or downward component selection path based on per-
formance, sample rate and power. The devices differ with re-
spect to their specified sampling rate and power consumption
which is reflected in their dynamic performance over frequency.
The AD9221/AD9223/AD9220 combine a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid and monolithic implementations at
a fraction of the power consumption and cost. Each device is a
complete, monolithic ADC with an on-chip, high performance,
low noise sample-and-hold amplifier and programmable voltage
reference. An external reference can also be chosen to suit the dc
accuracy and temperature drift requirements of the application.
The devices use a multistage differential pipelined architecture with
digital output error correction logic to provide 12-bit accuracy at
the specified data rates and to guarantee no missing codes over the
full operating temperature range.
The input of the AD9221/AD9223/AD9220 is highly flexible,
allowing for easy interfacing to imaging, communications, medi-
cal, and data-acquisition systems. A truly differential input
structure allows for both single-ended and differential input
interfaces of varying input spans. The sample-and-hold (SHA)
amplifier is equally suited for both multiplexed systems that
switch full-scale voltage levels in successive channels as well as
sampling single-channel inputs at frequencies up to and beyond
the Nyquist rate. Also, the AD9221/AD9223/AD9220 is well
AD9221/AD9223/AD9220–SPECIFICATIONS
DC SPECIFICATIONS
NOTESVREF =1 V.Including internal reference.Excluding internal reference.
(AVDD = +5 V, DVDD = +5 V, fSAMPLE = Max Conversion Rate, VREF = 2.5 V, VINB = 2.5 V, TMIN to TMAX unless
otherwise noted)
AC SPECIFICATIONS
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
AD9221/AD9223/AD9220
(AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)
(AVDD = +5 V, DVDD= +5 V, fSAMPLE = Max Conversion Rate, VREF = 1.0 V, VINB = 2.5 V, DC Coupled/Single-
Ended Input TMIN to TMAX unless otherwise noted)
AD9221/AD9223/AD9220
SWITCHING SPECIFICATIONS
NOTESThe clock period may be extended to 1 ms without degradation in specified performance @ +25°C.
Specifications subject to change without notice.
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, CL = 20 pF)
tCL tCHDATA
OUTPUT
INPUT
CLOCK
ANALOG
INPUTS2
Figure 1.Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead SOICJA = 71.4°C/WJC = 23°C/W
28-Lead SSOPJA = 63.3°C/WJC = 23°C/W
ORDERING GUIDE
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal differ-
ence between first and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
PIN CONNECTIONS
CLK
AVSS
AVDD
DVSS
DVDD
(LSB) BIT 12
BIT 11
BIT 10
CML
VINA
VINBBIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4REFCOM
CAPB
CAPT
BIT 3
BIT 2
(MSB) BIT 1
OTR
VREF
AVDD
AVSS
SENSE
PIN FUNCTION DESCRIPTIONS
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
AD9221/AD9223/AD9220
AD9221–Typical Characterization Curves
CODE
DNL – LSBs
Figure 2.Typical DNL
FREQUENCY – MHz
SINAD – dB
0.11.0
Figure 5.SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
FREQUENCY – MHz
THD– dB
–80
Figure 8.THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
(AVDD = +5 V, DVDD = +5 V, fSAMPLE = 1.5 MSPS, TA = +258C)
CODE
INL – LSBs
Figure 3.Typical INL
FREQUENCY – MHz
THD – dB
Figure 6.THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
SAMPLE RATE – MSPS
THD – dB
0.40.6
Figure 9.THD vs. Sample Rate
(AIN = –0.5 dB, fIN = 500 kHz,
VCM = 2.5 V)
CODE
HITS
N–1NN+1
Figure 4.“Grounded-Input”
Histogram (Input Span = 2 V p-p)
FREQUENCY – MHz
SINAD – dB
0.11.0
Figure 7.SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
AIN – dBFS
SNR/SFDR – dB
–20–100
Figure 10.SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 500 kHz, Input Span
= 2 V p-p, VCM = 2.5 V)
AD9223–Typical Characterization Curves
CODE
INL – LSBs
Figure 12.Typical INL

FREQUENCY – MHz
THD – dB
–100
Figure 15.THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)

SAMPLE RATE – MSPS
THD – dB
0.612356
Figure 18.THD vs. Sample Rate (AIN
= –0.5 dB, fIN = 500 kHz, VCM = 2.5 V)
(AVDD = +5 V, DVDD = +5 V, fSAMPLE = 3.0 MSPS, TA = +258C)
CODE
DNL – LSBs
Figure 11.Typical DNL

FREQUENCY – MHz
SINAD – dB
0.11.010.0
Figure 14.SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
FREQUENCY – MHz
THD – dB
–100
Figure 17.THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)

Figure 13.“Grounded-Input”
Histogram (Input Span = 2 V p-p)

Figure 16.SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
Figure 19.SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 1.5 MHz, Input
Span = 2 V p-p, VCM = 2.5 V)
AD9221/AD9223/AD9220
AD9220–Typical Characterization Curves(AVDD = +5 V, DVDD = +5 V, fSAMPLE = 10 MSPS, TA = +258C)
CODE
DNL – LSBs
Figure 20.Typical DNL
FREQUENCY – MHz
SINAD – dB
Figure 23.SINAD vs. Input Fre-
quency (Input Span = 2.0 V p-p,
VCM = 2.5 V)
FREQUENCY – MHz
THD – dB
–80
Figure 26.THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
CODE
INL – LSBs
Figure 21.Typical INL
FREQUENCY – MHz
THD – dB
Figure 24.THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
SAMPLE RATE – MSPS
THD – dB
–90
Figure 27.THD vs. Clock Frequency
(AIN = –0.5 dB, fIN = 1.0 MHz, VCM =
2.5 V)
CODE
HITS
N–1NN+1
Figure 22.“Grounded-Input”
Histogram (Input Span = 2 V p-p)
Figure 25.SINAD vs. Input Fre-
quency (Input Span = 5.0 V p-p,
VCM = 2.5 V)
Figure 28.SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 5.0 MHz, Input
Span = 2 V p-p, VCM = 2.5 V)
INTRODUCTION
The AD9221/AD9223/AD9220 are members of a high perfor-
mance, complete single-supply 12-bit ADC product family based
on the same CMOS pipelined architecture. The product family
allows the system designer an upward or downward component
selection path based on dynamic performance, sample rate, and
power. The analog input range of the AD9221/AD9223/AD9220
is highly flexible allowing for both single-ended or differential
inputs of varying amplitudes which can be ac or dc coupled.
Each device shares the same interface options, pinout and pack-
age offering.
The AD9221/AD9223/AD9220 utilize a four-stage pipeline
architecture with a wideband input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each
stage of the pipeline, excluding the last stage, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
amplifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers of the
AD9220ARS, AD9221 and AD9223 can be configured to
interface with +5 V or +3.3 V logic families, while the AD9220AR
can only be configured for +5 V logic.
The AD9221/AD9223/AD9220 use both edges of the clock in
their internal timing circuitry (see Figure 1 and specification
page for exact timing requirements). The A/D samples the ana-
log input on the rising edge of the clock input. During the clock
low time (between the falling edge and rising edge of the clock),
the input SHA is in the sample mode; during the clock high
time it is in hold. System disturbances just prior to the rising
edge of the clock and/or excessive clock jitter may cause the
input SHA to acquire the wrong value, and should be minimized.
The internal circuitry of both the input SHA and individual
pipeline stages of each member of the product family are opti-
mized for both power dissipation and performance. An inherent
tradeoff exists between the input SHA’s dynamic performance
and its power dissipation. Figures 29 and 30 shows this tradeoff
by comparing the full-power bandwidth and settling time of the
AD9221/AD9223/AD9220. Both figures reveal that higher
full-power bandwidths and faster settling times are achieved at
the expense of an increase in power dissipation. Similarly, a
tradeoff exists between the sampling rate and the power dissipated
in each stage.
As previously stated, the AD9220, AD9221 and AD9223 are
similar in most aspects except for the specified sampling rate,
power consumption, and dynamic performance. The product
and interface options. As a result, many of the application issues
and tradeoffs associated with these resulting configurations are
also similar. The data sheet is structured such that the designer
can make an informed decision in selecting the proper A/D and
optimizing its performance to fit the specific application.
FREQUENCY – MHz
AMPLITUDE – dB
Figure 29.Full-Power Bandwidth

Figure 30.Settling Time
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 31, a simplified model of the AD9221/AD9223/AD9220,
highlights the relationship between the analog inputs, VINA,
VINB, and the reference voltage, VREF. Like the voltage
applied to the top of the resistor ladder in a flash A/D converter,
the value VREF defines the maximum input voltage to the A/D
core. The minimum input voltage to the A/D core is automatically
defined to be –VREF.
Figure 31.AD9221/AD9223/AD9220 Equivalent Functional
AD9221/AD9223/AD9220
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily con-
figure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
VCORE = VINA – VINB(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF £ VCORE £ VREF(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9221/
AD9223/AD9220. The power supplies bound the valid operat-
ing range for VINA and VINB. The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V(3)
AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9221/
AD9223/AD9220, see Table IV.
Refer to Table I and Table II at the end of this section for a
summary of both the various analog input and reference
configurations.
ANALOG INPUT OPERATION
Figure 32 shows the equivalent analog input of the AD9221/
AD9223/AD9220 which consists of a differential sample-and-
hold amplifier (SHA). The differential input structure of the
SHA is highly flexible, allowing the devices to be easily config-
ured for either a differential or single-ended input. The dc
offset, or common-mode voltage, of the input(s) can be set to
accommodate either single-supply or dual supply systems. Also,
note that the analog inputs, VINA and VINB, are interchange-
able with the exception that reversing the inputs to the VINA
and VINB pins results in a polarity inversion.
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two condi-
tions: (1) the common-mode voltage is centered around mid
supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, QS1, being CMOS
switches whose RON resistance is very low but has some signal
dependency which causes frequency dependent ac distortion
while the SHA is in the track mode. The RON resistance of a
CMOS switch is typically lowest at its midsupply but increases
symmetrically as the input signal approaches either AVDD or
AVSS. A lower input signal voltage span centered at midsupply
reduces the degree of RON modulation.
Figure 32a compares the AD9221/AD9223/AD9220’s THD vs.
frequency performance for a 2 V input span with a common-
mode voltage of 1 V and 2.5 V. Note how each A/D with a
common-mode voltage of 1V exhibits a similar degradation in
THD performance at higher frequencies (i.e., beyond 750kHz).
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be domi-
nated by static nonlinearities such as INL and DNL. It is
important to note that these dc static nonlinearities are inde-
pendent of any RON modulation.
FREQUENCY – MHz
THD – dB
–50
Figure 32a.AD9221/AD9223/AD9220 THD vs. Frequency for
VCM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. Also, the
required input signal voltage span is reduced by a half which
further reduces the degree of RON modulation and its effects on
distortion.
The optimum noise and dc linearity performance for either differ-
ential or single-ended inputs is achieved with the largest input
signal voltage span (i.e., 5 V input span) and matched input
impedance for VINA and VINB. Note that only a slight degra-
dation in dc linearity performance exists between the 2 V andV input span as specified in the AD9221/AD9223/AD9220
Referring to Figure 32, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input imped-
ance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, CPIN, parasitic capacitance
CPAR, and the sampling capacitance, CS, is typically less thanpF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on CS to the new
input voltage. This action of charging and discharging CS,
averaged over a period of time and for a given sampling fre-
quency, FS, makes the input impedance appear to have a benign
resistive component. However, if this action is analyzed within
a sampling period (i.e., T = 1/FS), the input impedance is dy-
namic and hence certain precautions on the input drive source
should be observed.
The resistive component to the input impedance can be com-
puted by calculating the average charge that gets drawn by CH
from the input drive source. It can be shown that if CS is al-
lowed to fully charge up to the input voltage before switches QS1
are opened, then the average current into the input is the same
as if there were a resistor of 1/(CS FS) ohms connected between
the inputs. This means that the input impedance is inversely
proportional to the converter’s sample rate. Since CS is onlypF, this resistive component is typically much larger than that
of the drive source (i.e., 25 kW at FS = 10 MSPS).
If one considers the SHA’s input impedance over a sampling
period, it appears as a dynamic input impedance to the input
drive source. When the SHA goes into the track mode, the
input source should ideally provide the charging current through
RON of switch QS1 in an exponential manner. The requirement
of exponential charging means that the most common input
source, an op amp, must exhibit a source impedance that is both
low and resistive up to and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a
series inductor and resistor. When a capacitive load is switched
onto the output of the op amp, the output will momentarily
drop due to its effective output impedance. As the output re-
covers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA input
as shown in Figure 33. The series resistance helps isolate the op
amp from the switched-capacitor load.
Figure 33.Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several factors
applications may require a larger resistor value to reduce the
noise bandwidth or possibly limit the fault current in an over-
voltage condition. Other applications may require a larger
resistor value as part of an antialiasing filter. In any case, since
the THD performance is dependent on the series resistance
and the above mentioned factors, optimizing this resistor value
for a given application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance of
VINA and VINB. The degree of improvement is dependent on
the resistor value and the sampling rate. For series resistor
values greater than 100 W, the use of a matching resistor is
encouraged.
Figure 34 shows a plot for THD performance vs. RSERIES for
the AD9221/AD9223/AD9220 at their respective sampling rate
and Nyquist frequency. The Nyquist frequency typically repre-
sents the worst case scenario for an ADC. In this case, a high
speed, high performance amplifier (AD8047) was used as the
buffer op amp. Although not shown, the AD9221/AD9223/
AD9220 exhibits a slight increase in SNR (i.e. 1 dB to 1.5 dB)
as the resistance is increased from 0 kW to 2.56 kW due to its
bandlimiting effect on wideband noise. Conversely, it exhibits
slight decrease in SNR (i.e., 0.5 dB to 2 dB) if VINA and
VINB do not have a matched input resistance.
Figure 34. THD vs. RSERIES (fIN = FS/2, AIN = –0.5 dB, Input
Span = 2 V p-p, VCM = 2.5 V)
Figure 34 shows that a small RSERIES between 30 W and 50 W
provides the optimum THD performance for the AD9220.
Lower values of RSERIES are acceptable for the AD9223 and
AD9221 as their lower sampling rates provide a longer transient
recovery period for the AD8047. Note that op amps with lower
bandwidths will typically have a longer transient recovery
period and hence require a slightly higher value of RSERIES
and/or lower sampling rate to achieve the optimum THD
performance.
As the value of RSERIES increases, a corresponding increase in
distortion is noted. This is due to its interaction with the SHA’s
parasitic capacitor, CPAR, which has a signal dependency. Hence,
the resulting R-C time constant is signal dependent and conse-
quently a source of distortion.
AD9221/AD9223/AD9220
other comparator controls internal circuitry which will disable
the reference amplifier if the SENSE pin is tied AVDD. Dis-
abling the reference amplifier allows the VREF pin to be driven
by an external voltage reference.
Figure 35.Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9221/AD9223/AD9220 appear on the CAPT and CAPB
pins. For proper operation when using the internal or an exter-
nal reference, it is necessary to add a capacitor network to de-
couple these pins. Figure 36 shows the recommended
decoupling network. This capacitive network performs the
following three functions: (1) along with the reference ampli-
fier, A2, it provides a low source impedance over a large fre-
quency range to drive the A/D internal circuitry, (2) it provides
the necessary compensation for A2, and (3) it bandlimits the
noise contribution from the reference. The turn-on time of the
reference voltage appearing between CAPT and CAPB is ap-
proximately 15ms and should be evaluated in any power-
down mode of operation.
Figure 36.Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4 respec-
tively in which the input span can be varied between 2V and 5V.
Note that those samples within the pipeline A/D during any
Figure 29. For noise sensitive applications, the excessive band-
width may be detrimental and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
A/D’s input by forming a low-pass filter. Note, however, that
the combination of this series resistance with the equivalent
input capacitance of the AD9221/AD9223/AD9220 should be
evaluated for those time-domain applications that are sensitive
to the input signal’s absolute settling time. In applications where
harmonic distortion is not a primary concern, the series resis-
tance may be selected in combination with the SHA’s nominal
16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9221/AD9223/AD9220, a lower series resis-
tance can be selected to establish the filter’s cutoff frequency
while not degrading the distortion performance of the device.
The shunt capacitance also acts like a charge reservoir, sinking
or sourcing the additional charge required by the hold capacitor,
CH, further reducing current transients seen at the op amp’s
output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9221/AD9223/AD9220 should be evaluated. To
optimize performance when noise is the primary consideration,
increase the shunt capacitance as much as the transient response
of the input signal will allow. Increasing the capacitance too
much may adversely affect the op amp’s settling time, frequency
response, and distortion performance.
REFERENCE OPERATION
The AD9221/AD9223/AD9220 contain an onboard bandgap
reference that provides a pin-strappable option to generate either a
1 V or 2.5 V output. With the addition of two external resistors,
the user can generate reference voltages other than 1 V and
2.5 V. Another alternative is to use an external reference for
designs requiring enhanced accuracy and/or drift performance.
See Table II for a summary of the pin-strapping options for the
AD9221/AD9223/AD9220 reference configurations.
Figure 35 shows a simplified model of the internal voltage refer-
ence of the AD9221/AD9223/AD9220. A pin-strappable refer-
ence amplifier buffers a 1 V fixed reference. The output from
the reference amplifier, A1, appears on the VREF pin. The
voltage on the VREF pin determines the full-scale input span of
the A/D. This input span equals,
Full-Scale Input Span = 2 · VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators which monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is con-
nected to the internal resistor network thus providing a VREF
of 2.5 V. If the SENSE pin is tied to the VREF pin via a short
Table I.Analog Input Configuration Summary
NOTEVINA and VINB can be interchanged if signal inversion is required.
Table II.Reference Configuration Summary
AD9221/AD9223/AD9220
amps which may otherwise have been constrained by headroom
limitations, (3) Differential operation minimizes even-order
harmonic products, and (4) Differential operation offers noise
immunity based on the device’s common-mode rejection. Fig-
ure 37 depicts the common-mode rejection of the three devices.
As is typical of most CMOS devices, exceeding the supply
limits will turn on internal parasitic diodes resulting in transient
currents within the device. Figure 38 shows a simple means of
clamping an ac or dc coupled single-ended input with the addi-
tion of two series resistors and two diodes. An optional capaci-
tor is shown for ac coupled applications. Note that a larger
series resistor could be used to limit the fault current through
D1 and D2 but should be evaluated since it can cause a degra-
dation in overall performance. A similar clamping circuit could
also be used for each input if a differential input signal is being
applied.
Figure 38.Simple Clamping Circuit
SINGLE-ENDED MODE OF OPERATION
The AD9221/AD9223/AD9220 can be configured for single-
ended operation using dc or ac coupling. In either case, the
input of the A/D must be driven from an operational amplifier
that will not degrade the A/D’s performance. Because the A/D
operates from a single-supply, it will be necessary to level-shift
ground-based bipolar signals to comply with its input require-
ments. Both dc and ac coupling provide this necessary func-
tion, but each method results in different interface issues which
may influence the system design and performance.
DC COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc
coupled to the AD9221/AD9223/AD9220. An operational
amplifier can be configured to rescale and level shift the input
signal so that it is compatible with the selected input range of
the A/D. The input range to the A/D should be selected on the
basis of system performance objectives as well as the analog
power supply availability since this will place certain constraints
on the op amp selection.
Many of the new high performance op amps are specified for
only –5 V operation and have limited input/output swing
capabilities. Hence, the selected input range of the AD9221/
AD9223/AD9220 should be sensitive to the headroom require-
ments of the particular op amp to prevent clipping of the sig-
nal. Also, since the output of a dual supply amplifier can swing
below –0.3 V, clamping its output should be considered in
some applications.
In some applications, it may be advantageous to use an op amp
specified for single supply +5 V operation since it will inher-
ently limit its output swing to within the power supply rails.
DRIVING THE ANALOG INPUTS
INTRODUCTION
The AD9221/AD9223/AD9220 has a highly flexible input struc-
ture allowing it to interface with single-ended or differential
input interface circuitry. The applications shown in sections
Driving the Analog Inputs and Reference Configurations, along
with the information presented in Input and Reference Over-
view of this data sheet, give examples of both single-ended and
differential operation. Refer to Tables I and II for a list of the
different possible input and reference configurations and their
associated figures in the data sheet.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power supply
options. For example, a dc coupled single-ended input would
be appropriate for most data acquisition and imaging applica-
tions. Also, many communication applications which require a
dc coupled input for proper demodulation can take advantage of
the excellent single-ended distortion performance of the AD9221/
AD9223/AD9220. The input span should be configured such
that the system’s performance objectives and the headroom
requirements of the driving op amp are simultaneously met.
Alternatively, the differential mode of operation with a trans-
former coupled input provides the best THD and SFDR perfor-
mance over a wide frequency range. This mode of operation
should be considered for the most demanding spectral-based
applications which allow ac coupling (e.g., Direct IF to Digital
Conversion).
Single-ended operation requires that VINA be ac or dc coupled
to the input signal source while VINB of the AD9221/AD9223/
AD9220 be biased to the appropriate voltage corresponding to a
midscale code transition. Note that signal inversion may be
easily accomplished by transposing VINA and VINB. The rated
specifications for the AD9221/AD9223/AD9220 are characterized
using single-ended circuitry with input spans of 5 V and 2 V as well
as VINB = 2.5 V.
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are in and out of
phase versions of the input signal. Differential operation of the
AD9221/AD9223/AD9220 offers the following benefits: (1)
Signal swings are smaller and therefore linearity requirements
placed on the input signal source may be easier to achieve, (2)
Signal swings are smaller and therefore may allow the use of op
CMR – dB

Partno	Mfg	Dc	Qty	Available	Descript
AD9220AR	AD	N/a	1000	avai	Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9220ARS	AD	N/a	29	avai	Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9221AR	N/A	N/a	180	avai	Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9223AR	ADI	N/a	5	avai	Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9223ARS	ADI	N/a	190	avai	Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters