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AD9218BST-105-AD9218BST-40-AD9218BST-65-AD9218BST-80
10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter
REV.0
FUNCTIONAL BLOCK DIAGRAM
10-Bit, 40/65/80/105 MSPS
3 V Dual A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dual 10-Bit, 40 MSPS, 65 MSPS, 80 MSPS, and
105MSPS ADC
Low Power: 275 mW at 105 MSPS per Channel
On-Chip Reference and Track/Holds
300 MHz Analog Bandwidth Each Channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p Analog Input Range Each Channel
Single 3.0 V Supply Operation (2.7 V–3.6 V)
Power-Down Mode for Single Channel Operation
Two’s Complement or Offset Binary Output Mode
Output Data Alignment Mode
Pin-Compatible with 8-Bit AD9288
–75 dBc Crosstalk between Channels
APPLICATIONS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
Ultrasound Equipment
GENERAL DESCRIPTIONThe AD9218 is a dual 10-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full operation. No external
reference or driver components are required for many applica-
tions. The digital outputs are TTL/CMOS-compatible and a
separate output power supply pin supports interfacing with
3.3V or 2.5 V logic.
The clock input is TTL/CMOS-compatible and the 10-bit
digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combi-
nation of power-down modes, digital data formats and digital
data timing schemes. In power-down mode, the digital outputs
are driven to a high-impedance state.
Fabricated on an advanced CMOS process, the AD9218 is
available in a 48-lead surface-mount plastic package (7 × 7 mm
LQFP) specified over the industrial temperature range (–40°C
to +85°C).
PRODUCT HIGHLIGHTSLow Power—Just 275 mW power dissipation per channel at
105MSPS. Other speed grade proportionally scaled down while
maintaining high ac performance.
Pin Compatibility Upgrade—Allows easy migration from 8-bit
to 10-bit. Pin-compatible with the 8-bit AD9288 dual ADC.
Ease of Use—On-chip reference and user controls provide flex-
ibility in system design.
High Performance—Maintain 54dB SNR at 105 MSPS with a
Nyquist input.
Channel Crosstalk—Very low at –75dBc.
AD9218–SPECIFICATIONS
DC SPECIFICATIONSNOTESNo Missing Codes across industrial temperature range guaranteed for -40 MSPS, -65 MSPS, and -80 MSPS grades. No missing codes at room temperature guaran-
teed for -105 grade.Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) -65 Grade in 2 V p-p range, -40, -85, -105 Grades in
1 V p-p range.(AIN – AIN) = ±0.5 V in 1 V range (full scale), (AIN – AIN) = ±1 V in 2 V range (full scale).AC Power Dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, CLOAD = 5 pF.DC Power Dissipation measured with rated encode and a dc analog input (Outputs Static, IVDD = 0)In power-down state IVDD = ±10 µA typical (all grades).
Specifications subject to change without notice.
(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
AD9218
DIGITAL SPECIFICATIONSSpecifications subject to change without notice.
AC SPECIFICATIONS
(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
AD9218–SPECIFICATIONS
SWITCHING SPECIFICATIONSNOTES
*tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times measured from 10% to 90%.
Specifications subject to change without notice.
Figure 1.Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
(VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.)
Figure 2.Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
Figure 3.Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
