AD9216BCPZ-65 ,3 V, 10-bit, 65 MSPS dual A/D converterSPECIFICATIONS Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 ..
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ADS7804P ,Brown Corporation - 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7804P ,Brown Corporation - 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7804P ,Brown Corporation - 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
AD9216BCPZ-65-AD9216BCPZRL7-65
3 V, 10-bit, 40 MSPS dual A/D converter
10-Bit, 65/80/105 MSPS
FEATURES
Integrated Dual 10-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist, AD9216-105)
SFDR = 75 dBc (to Nyquist, AD9216-105)
Low Power: 280mW at 105MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 75dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
3G, Radio Point-to-Point, LMDS, MMDS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION The AD9216 is a dual, 3 V, 10-bit, 65/80/105 MSPS analog-to-
digital converter. It features dual high performance sample-and hold amplifiers and an integrated voltage reference. The
AD9216 uses a multistage differential pipelined architecture
with output error correction logic to provide 10-bit accuracy and guarantee no missing codes over the full operating
temperature range at up to 105 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the AD9216 (all speed grades) and can compensate for wide
variations in the clock duty cycle, allowing the converters to
maintain excellent performance. The digital output data is presented in either straight binary or twos complement format.
Out-of-range signals indicate an overflow condition, which can
be used with the most significant bit to determine low or high
overflow.
Fabricated on an advanced CMOS process, the AD9216 is
available in a space saving 64-lead LFCSP (9x9) and is
specified over the industrial temperature range (–40°C to
+85°C). D9A-D0A
AGND
VIN- _A
CLK_A
VIN+_A
DCSSENSE
REFT_A
AVDDVIN-_BVIN+_BD10B-D0B
MUX_SELECT
CLK_B
AGND
DRGND
SHARED_REF
PWDN_A
DFS
REFB_A
REFT_B
REFB_B
PWDN_B
OTR_B
OEB_B
OEB_A
OTR_A
VREF
DRVDD
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS 1. Pin compatible with AD9238, dual 12-bit
20/40/65MSPS ADC and AD9248, dual 14-bit
20/40/65MSPS ADC.
2. Speed grade options off 105 MSPS, 80 MSPS, and
65 MSPS allow flexibility between power, cost, and
performance to suit an application.
3. Low power consumption:
AD9216-105: 105 MSPS = 280 mW
AD9216-80: 80 MSPS = 238 mW
AD9216-65: 65 MSPS = 215mW
4. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and
can be configured for single-ended or differential operation.
5. Typical channel isolation of 75 dB @ fIN = 10 MHz.
6. The clock duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.
TABLE OF CONTENTS General Description..............................................................1
Product Highlights................................................................1
DC Specifications (Continued).............................................4
Switching Specifications.......................................................4
AC Specifications.................................................................5
Absolute Maximum Ratings.....................................................7
ESD Caution.........................................................................7
Terminology........................................................................10
Typical Performance CharacteristiC PLOTS (TBD)..............12
Equivalent Circuits.................................................................13
Theory of Operation............................................................13
Analog Input.......................................................................13
Clock Input and Considerations..........................................15
Power Dissipation and Standby Mode................................15
Digital Outputs....................................................................15
Timing................................................................................16
Data Format........................................................................16
Voltage Reference...............................................................17
Evaluation Board Diagrams (TBD)........................................19
Outline Dimensions................................................................20
REVISION HISTORY PrA: Initial Version
PrB: included specification tables, ordering guide, package and pin configuration and Theory of operation sections.
PrC: Corrected pin configuration figure (Fig3) pin naming errors , updated supply spec, corrected timing diagram and latency.
PrD: Removed 120MSPS Grade, Updated DCS,OEB_B pin descriptions, updated input referred noise, Demux Timing Diagram needs
updating
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.) ±0.3 ±0.30 ±1.0 ±1.0 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±15 ±15 ±30 ±30 ±5 ±5 0.8 0.8 ±2.5 ±2.5 0.1 0.1 0.8 0.8 0.4 0.4 1 1 2 2 2 2 7 7 3.0 3.0 2.5 2.5 TBD/TBD TBD TBD/TBD TBD ±0.01 ±0.01 TBD/TBD TBD 215/238 280 1/1 1
Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate.
DC SPECIFICATIONS (CONTINUED)
Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.) 2 2
LOGIC OUTPUTS1
DRVDD = 2.5V
High Level Output Voltage
Low Level Output Voltage
Output Voltage Levels measured with 5 pF load on each output. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications Typ Typ 4.8 4.8 6 6 1.0 1.0 0.5 0.5 2.5 2.5 The AD9216 has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC xx). 2 Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
PD
ANALOG
INPUT
CLK
DATA
OUT
N–1N+1
N+2
N+3
N+4N+5N+6
N+7
N+8
AC SPECIFICATIONS
Table 4. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.) 58 57 58 58 57 57 57 56 58 57 58 58 57 56 56 55 9.4 9.3 9.4 9.4 9.3 9.1 9.1 8.9 -70.0 -70.0 -69.0 -70.0 -69.0 -68.0 -67.0 -66.0 -75.0 -74.0
SPURIOUS FREE DYNAMIC RANGE
fINPUT = 2.4 MHz 75.0 75.0
fINPUT = 19.6 MHz 75.0 TBD 75.0
fINPUT = 32.5 MHz 74.0
-80.0 Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9216 Absolute Maximum Ratings1
Parameter Unit Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. Typical thermal impedances (64-lead LQFP); JA = 54°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing. Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Table 6. ORDERING GUIDE AGND
VIN-_A
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
AVDD
AGND
VIN+_B
VIN-_B
VIN+_A
AGND
D2_A
D0_A
DNC
DNC
DNC
DNC
DRVDD
DRGND
OTR_B
D9_B(MSB)
D8_B
D7_B
D6_B
D5_B
D1_AD4_B
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
TERMINOLOGY
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is manifested as noise on the input to the A/D converter.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-Bits resolution indicates that all 2048 codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale
from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels relative to the peak carrier
signal (dBc).
Effective Number of Bits (ENOB)
Using the following formula:
effective number of bits for a
device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels relative to the peak carrier
signal (dBc).
Spurious Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited to Nyquist sampling. Higher sampled frequencies will be
aliased down into the first Nyquist zone (DC - fCLOCK/2) on the
output of the ADC. Care must be taken that the bandwidth of the sampled signal does not overlap Nyquist zones and alias
onto itself. Nyquist sampling performance is limited by the
bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the A/D
converter to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale,
or from 10% below negative full scale to 10% below positive full scale. 026761ENOB..
