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AD9215BCPZ-65
10-Bit, 65/80/105 MSPS, 3V A/D Converter
10-Bit, 65/80/105 MSPS,
3 V A/D Converter
Rev. A
FEATURES
Single 3 V supply operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist)
SFDR = 77 dBc (to Nyquist)
Low power ADC core: 96 mW at 65 MSPS, 104 mW
@ 80 MSPS, 120 mW at 105 MSPS
Differential input with 300 MHz bandwidth
On-chip reference and sample-and-hold amplifier
DNL = ±0.25 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
FUNCTIONAL BLOCK DIAGRAM
VIN+
VIN–
REFT
REFB
D9 (MSB)VREF
SENSE
Figure 1.
PRODUCT DESCRIPTION The AD9215 is a family of monolithic, single 3 V supply, 10-bit,
65/80/105 MSPS analog-to-digital converters (ADC). This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9215 uses a multistage differential
pipelined architecture with output error correction logic to pro-
vide 10-bit accuracy at 105 MSPS data rates and to guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential sample-and-hold ampli-
fier (SHA) allows for a variety of user-selectable input ranges
and offsets including single-ended applications. It is suitable for
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling single-channel inputs at
frequencies well beyond the Nyquist rate. Combined with
power and cost savings over previously available ADCs, the
AD9215 is suitable for applications in communications, imag-
ing, and medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer compensates for wide variations in the
clock duty cycle while maintaining excellent performance. The digital
output data is presented in straight binary or twos complement for-
mats. An out-of-range signal indicates an overflow condition, which
can be used with the MSB to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9215 is avail-
able in both a 28-lead surface-mount plastic package and a
32-lead chip scale package and is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS 1. The AD9215 operates from a single 3 V power supply and
features a separate digital output driver supply to accom-
modate 2.5 V and 3.3 V logic families.
2. Operating at 105 MSPS, the AD9215 core ADC consumes
a low 120 mW; at 80 MSPS, the power dissipation is 104
mW; and at 65 MSPS, the power dissipation is 96 mW.
3. The patented SHA input maintains excellent performance
for input frequencies up to 200 MHz and can be config-
ured for single-ended or differential operation.
4. The AD9215 is part of several pin compatible 10-, 12-, and
14-bit low power ADCs. This allows a simplified upgrade
from 10 bits to 12 bits for systems up to 80 MSPS.
5. The clock duty cycle stabilizer maintains converter per-
formance over a wide range of clock pulse widths.
6. The out of range (OR) output bit indicates when the signal
is beyond the selected input range.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................6
Explanation of Test Levels...........................................................6
ESD Caution..................................................................................6
Pin Configurations and Function Descriptions...........................7
Equivalent Circuits.......................................................................8
Definitions of Specifications.......................................................8
Typical Performance Characteristics...........................................10
Applying the AD9215 Theory of Operation...............................14
Clock Input and Considerations..............................................15
Evaluation Board........................................................................18
Outline Dimensions.......................................................................33
Ordering Guide...........................................................................34
REVISION HISTORY
2/04—Data Sheet Changed from a REV. 0 to a REV. A Renumbered Figures and Tables..............................UNIVERSAL
Changes to Product Title................................................................1
Changes to Features........................................................................1
Changes to Product Description...................................................1
Changes to Product Highlights.....................................................1
Changes to Specifications...............................................................2
Changes to Figure 2.........................................................................4
Changes to Figures 9 to 11...........................................................10
Added Figure 14............................................................................10
Added Figures 16 and 18..............................................................11
Changes to Figures 21 to 24 and 25 to 26...................................12
Deleted Figure 25...........................................................................12
Changes to Figures 28 and 29......................................................13
Changes to Figure 31.....................................................................14
Changes t0 Figure 35.....................................................................16
Changes to Figures 50 through 58...............................................26
Added Table 11..............................................................................31
Updated Outline Dimensions......................................................32
Changes to Ordering Guide.........................................................33
5/03—Revision 0: Initial Version SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise
noted.
Table 1. DC Specifications 1 With a 1.0 V internal reference.
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.
Table 2. AC Specifications Table 3. Digital Specifications Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications 02874-A
tPD
ANALOG
INPUT
CLK
DATA
OUT
N–1N+1
N+2
N+3
N+4
N+5N+6
N+7
N+8
Figure 2. Timing Diagram
