AD9203ARU Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9203ARU
10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter
REV. 0
10-Bit, 40 MSPS, 3 V, 74 mW
A/D Converter
FEATURES
CMOS 10-Bit 40 MSPS Sampling A/D Converter
Power Dissipation: 74 mW (3 V Supply, 40 MSPS)
17 mW (3 V Supply, 5 MSPS)
Operation Between 2.7 V and 3.6 V Supply
Differential Nonlinearity: 60.25 LSB
Power-Down (Standby) Mode, 0.65 mW
ENOB: 9.55 @ fIN = 20 MHz
Out-of-Range Indicator
Adjustable On-Chip Voltage Reference
IF Undersampling up to fIN = 130 MHz
Input Range: 1 V to 2 V p-p Differential or Single-Ended
Adjustable Power Consumption
Internal Clamp Circuit
APPLICATIONS
CCD Imaging
Video
Portable Instrumentation
IF and Baseband Communications
Cable Modems
Medical Ultrasound
PRODUCT DESCRIPTION
The AD9203 is a monolithic low power, single supply, 10-bit,
40 MSPS analog-to-digital converter, with an on-chip voltage
reference. The AD9203 uses a multistage differential pipeline
architecture and guarantees no missing codes over the full oper-
ating temperature range. Its input range may be adjusted be-
tween 1 V and 2 V p-p.
The AD9203 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of an application.
An external resistor can be used to reduce power consumption
when operating at lower sampling rates. This yields power sav-
ings for users who do not require the maximum sample rate.
This feature is especially useful at sample rates far below 40
MSPS. Excellent performance is still achieved at reduced power.
For example, 9.7 ENOB performance may be realized with only
17 mW of power, using a 5 MHz clock.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary or
twos complementary output format by using the DFS pin. An
out-of-range signal (OTR) indicates an overflow condition that
can be used with the most significant bit to determine over or
under range.
The AD9203 can operate with a supply range from 2.7 V to
3.6 V, attractive for low power operation in high speed por-
table applications.
The AD9203 is specified over industrial (–40°C to +85°C)
temperature ranges and is available in a 28-lead TSSOP
package.
PRODUCT HIGHLIGHTS
Low Power
The AD9203 consumes 74 mW on a 3 V supply operating at
40 MSPS. In standby mode, power is reduced to 0.65 mW.
High Performance
Maintains better than 9.55 ENOB at 40 MSPS input signal
from dc to Nyquist.
Very Small Package
The AD9203 is available in a 28-lead TSSOP.
Programmable Power
The AD9203 power can be further reduced by using an external
resistor at lower sample rates.
Built-In Clamp Function
Allows dc restoration of video signals.
FUNCTIONAL BLOCK DIAGRAM
AD9203–SPECIFICATIONS
(AVDD = +3 V, DRVDD = +3V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, Internal 1 V
Reference, PWRCON = AVDD, 50% clock duty cycle, TMIN to TMAX unless otherwise noted.)
ANALOG INPUT
AD9203
NOTESDifferential Input (2 V p-p).The AD9203 will convert at clock rates as low as 20 kHz.
Specifications subject to change without notice.
N–7N–6N–5N–4N–3N–2N–1NN+1
N–1N+1
N+2
N+3
N+4N+5
N+6
TOD = 3ns MIN
(CLOAD = 20pF)
ANALOG
INPUT
CLOCK
DATA
OUT
7ns MAX
Figure 1.Timing Diagram
AD9203
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
THERMAL CHARACTERISTICS
28-Lead TSSOPJA = 97.9°C/WJC = 14.0°C/W
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
AD9203
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs
1/2 LSB before the first code transition. “Positive full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
The deviation is measured from the middle of each particular
code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL, NO
MISSING CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes respectively, must be present over all operating ranges.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
OFFSET ERROR
First transition should occur for an analog value 1/2 LSB above
–full scale. Offset error is defined as the deviation of the actual
transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2LSB above –full scale. The last transition should occur for
an analog value 1 1/2 LSB below the +full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided on every rising edge.
(AVDD = +3 V, DRVDD = +3 V, FS = 40 MSPS, 1 V Internal Reference, PWRCON = AVDD, 50% Duty Cycle, unless otherwise noted)
INPUT FREQUENCY – MHz012020
SNR – dB6080100
Figure 2.SNR vs. Input Frequency and Configuration
INPUT FREQUENCY – MHz12020
SINAD – dB6080100
ENOB
Figure 3.SINAD vs. Input Frequency and Configuration
INPUT FREQUENCY – MHz
THD – dB6080100
–40
Figure 4.THD vs. Input Frequency and Amplitude (Differ-
ential Input VREF = 0.5 V)
Figure 5.SFDR vs. Input Frequency and Configuration
Figure 6.THD vs. Input Frequency and Configuration
Figure 7.THD vs. Input Frequency and Amplitude (Differ-
ential Input VREF = 1 V)
AD9203
N–1N
1.2E+07
1.0E+07
8.0E+06
4.0E+06
6.0E+06
0.0E+00
2.0E+06
N+1
CODE
HITS
Figure 8.Grounded Input Histogram

SAMPLE RATE – MSPS
+SNR/–THD – dB306050
Figure 9.SNR and THD vs. Sample Rate (fIN = 20 MHz)
LSB
Figure 10.Typical INL Performance
LSB
Figure 11.Typical DNL Performance

0E+020E+62.5E+65E+67.5E+610E+6
12.5E+615E+617.5E+6
–120.0
Figure 12.Single Tone Frequency Domain Performance
(Input Frequency = 10 MHz, Sample Rate = 40 MSPS 2 V
Differential Input, 8192 Point FFT)
SUPPLY VOLTAGE – V
+SNR/–THD – dB
3.03.54.0
Figure 13.THD vs. Power Supply (fIN = 20 MHz, Sample
INPUT FREQUENCY – MHz1000100
AMPLITUDE – dB
Figure 14.Full Power Bandwidth
OFF-TIME – ms
WAKE-UP TIME –
1000
Figure 15.Wake-Up Time vs. Off Time (VREF Decoupling
= 10 mF)
TEMPERATURE – 8C
REF
ERROR – %
–0.4–20020406080100
Figure 16.Reference Voltage vs. Temperature
APPLYING THE AD9203
THEORY OF OPERATION
The AD9203 implements a pipelined multistage architecture to
achieve high sample rates while consuming low power. The
AD9203 distributes the conversion over several smaller A/D
subblocks, refining the conversion with progressively higher
accuracy as it passes the results from stage to stage. As a conse-
quence of the distributed conversion, the AD9203 requires a
small fraction of the 1023 comparators used in a traditional
10-bit flash-type A/D. A sample-and-hold function within each
of the stages permits the first stage to operate on a new input
sample while the remaining stages operate on preceding samples.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each one of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The input of the AD9203 incorporates a novel structure that
merges the input sample and hold amplifier (SHA) and the first
pipeline residue amplifier into a single, compact switched ca-
pacitor circuit. This structure achieves considerable noise and
power savings over a conventional implementation that uses
separate amplifiers by eliminating one amplifier in the pipeline.
By matching the sampling network of the input SHA with the
first stage flash A/D, the AD9203 can sample inputs well beyond
the Nyquist frequency with no degradation in performance.
Sampling occurs on the falling edge of the clock.
OPERATIONAL MODES
The AD9203 may be connected in several input configurations
(see Table I).
The AD9203 may be driven differentially from a source that
keeps the signal peaks within the power supply rails.
Alternatively, the input may be driven into AINP or AINN from
a single-ended source. The input span will be 2· the programmed
reference voltage. One input will accept the signal, while the
opposite input will be set to midscale by connecting it to the
internal or an external reference. For example, a 2 V p-p signal
may be applied to AINP while a 1 V reference is applied to AINN.
The AD9203 will then accept a signal varying between 2 V and
0 V. See Figures 17, 18 and 19 for more details.
The AD9203’s single-ended (ac-coupled) input may also be
clamped to ground by the AD9203’s internal clamp switch. This
is accomplished by connecting the CLAMP pin to AINN or AINP.
Digital output formats may be configured in binary and twos
complement. This is determined by the potential on the DFS
pin. If the pin is set to Logic “0,” the data will be in straight
binary format. If the pin is asserted to Logic “1,” the data will be in
twos complement format.
Power consumption may be reduced by placing a resistor be-
tween PWRCON and AVSS. This may be done to conserve
power when not encoding high speed analog input frequencies
AD9203
INPUT AND REFERENCE OVERVIEW
Like the voltage applied to the top of the resistor ladder in a
flash A/D converter, the value VREF defines the maximum
input voltage to the A/D core. The minimum input voltage to the
A/D core is automatically defined to be –VREF.
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the AINP and AINN input
pins. Therefore, the equation,
VCORE = AINP – AINN(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF £ VCORE £ VREF(2)
where VREF is the voltage at the VREF pin.
The actual span (AINP – AINN) of the ADC is –VREF.
While an infinite combination of AINP and AINN inputs exist
that satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9203. The power
supplies bound the valid operating range for AINP and AINN.
The condition,
AVSS – 0.3 V < AINP < AVDD + 0.3 V(3)AVSS – 0.3 V < AINN < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +3 V,
defines this requirement. The range of valid inputs for AINP
and AINN is any combination that satisfies both Equations 2
and 3.
INTERNAL REFERENCE CONNECTION
A comparator within the AD9203 will detect the potential of the
VREF pin. If REFSENSE is grounded, the reference amplifier
switch will connect to the resistor divider (see Figure 17). That
will make VREF equal to 1 V. If resistors are placed between
VREF, REFSENSE and ground, the switch will be connected to
the REFSENSE position and the reference amplitude will de-
pend on the external programming resistors (Figure 19). If
REFSENSE is tied to VREF, the switch will also connect to
REFSENSE and the reference voltage will be 0.5 V (Figure 18).
Table I.Modes
ADC will equal the twice voltage at the reference pin for both
an internal or external reference.
Figure 17 illustrates the input configured with a 1 V reference.
This will set the single-ended input of the AD9203 in the 2 V
span (2 · VREF). This example shows the AINN input is tied
to the 1 V VREF. This will configure the AD9203 to accept a
2 V input centered around 1 V.10mF
AINP
REFSENSE
0.1mF
10mF
Figure 17.Internal Reference Set for a 2 V Span
Figure 18 illustrates the input configured with a 0.5 V reference.
This will set the single ended input of the ADC in a 1 V span
(2 · VREF). The AINN input is tied to the 0.5 VREF. This will
configure the AD9203 to accept a 1 V input centered around
0.5 V.

Partno	Mfg	Dc	Qty	Available	Descript
AD9203ARU	ADI	N/a	415	avai	10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter