AD9200ARS-AD9200JRS-AD9200JST-AD9200JSTRL-AD9200KST-AD9200KSTRL Fast Delivery |IC PHOENIX CO.,LIMITED

AD9200JSTRL ,Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converterapplications.Out-of-Range IndicatorThe AD9200 is specified over the industrial (–40

AD9200ARS-AD9200JRS-AD9200JST-AD9200JSTRL-AD9200KST-AD9200KSTRL
Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
REV.EComplete 10-Bit, 20 MSPS, 80 mW
CMOS A/D Converter
FUNCTIONAL BLOCK DIAGRAMAIN
REFTF
REFBF
REFSENSE
OTR
(MSB)
(LSB)
VREF
DRVDDAVDDCLK
DRVSS
REFTS
AVSS
REFBSTHREE-
STATE
MODE
STBY
CLAMP
CLAMP
FEATURES
CMOS 10-Bit, 20 MSPS Sampling A/D Converter
Pin-Compatible with AD876
Power Dissipation: 80 mW (3 V Supply)
Operation Between 2.7 V and 5.5 V Supply
Differential Nonlinearity: 0.5 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
PRODUCT DESCRIPTION
The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9200 uses a multistage
differential pipeline architecture at 20 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the AD9200 has been designed to ease the devel-
opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
The sample-and-hold (SHA) amplifier is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and beyond the Nyquist rate. AC coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit (AD9200ARS, AD9200KST). The dynamic per-
formance is excellent.
The AD9200 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9200 can operate with supply range from 2.7 V to
5.5V, ideally suiting it for low power operation in high speed
portable applications.
The AD9200 is specified over the industrial (–40°C to +85°C)
and commercial (0°C to +70°C) temperature ranges.
PRODUCT HIGHLIGHTS
Low Power
The AD9200 consumes 80 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to belowmW.
Very Small Package
The AD9200 is available in both a 28-lead SSOP and 48-lead
LQFP packages.
Pin Compatible with AD876
The AD9200 is pin compatible with the AD876, allowing older
designs to migrate to lower supply voltages.
300 MHz On-Board Sample-and-Hold
The versatile SHA input can be configured for either single-
ended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9200’s input range.
Built-In Clamp Function
Allows dc restoration of video signals with AD9200ARS and
AD9200KST.
AD9200–SPECIFICATIONS
(AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted)
DIGITAL OUTPUTS
LOGIC OUTPUT (with DRVDD = 3 V)
LOGIC OUTPUT (with DRVDD = 5 V)
CLOCKING
NOTESSee Figures 1a and 1b.Available only in AD9200ARS and AD9200KST.
Specifications subject to change without notice.
Figure 1a. Figure 1b.
AD9200
AD9200
DRVDD
AVSS
DRVSS
DRVSS
AVDD
AVDD
AVSS
AVSS
AVDD
REFTF
REFTS
AVDD
AVDD
AVSS
REFBS
REFBF
AVDD
AVDD
AVSS
AVSS
AVDD
AVSS
AVSS
AVDD
AVSS
AVDD
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
*RS = Shrink Small Outline; ST = Thin Quad Flatpack.
Figure 2. Equivalent CircuitsD0–D9, OTRb.Three-State, Standby, Clampc.CLKAINe.ReferenceCLAMPINg.MODEh.REFSENSEi.VREF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
28-Lead Shrink Small Outline (SSOP)
AVSS
REFBS
VREF
AIN
AVDD
DRVDD
REFTF
MODE
REFBFD2CLAMP
CLAMPIN
REFTS
OTR
DRVSS
REFSENSE
CLK
THREE-STATE
STBY
48-Lead Plastic Thin Quad Flatpack (LQFP)
AVDDVREFNCNCNCAVSSNCNCAINNC
REFBS
REFBF
MODE
REFTFNC
OTR
DRVSS
NC = NO CONNECT
REFTS
CLAMPIN
CLAMP
REFSENSENC
CLK
THREE-STATE
STBYNC
DRVDD
AD9200
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale”. The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
Typical Characterization Curves
CODE OFFSET
DNL
–0.5
Figure 3.Typical DNL
CODE OFFSET
INL
–0.5
Figure 4.Typical INL
Offset Error
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
Gain Error
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.
INPUT FREQUENCY – Hz
1.00E+051.00E+081.00E+061.00E+07
SNR– dB
Figure 5.SNR vs. Input Frequency
1.00E+051.00E+081.00E+06
SINAD – dB
1.00E+07
INPUT FREQUENCY – Hz
Figure 6.SINAD vs. Input Frequency
(AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)
1.00E+051.00E+081.00E+061.00E+07
THD – dB
INPUT FREQUENCY – Hz
–55
Figure 7.THD vs. Input Frequency
CLOCK FREQUENCY – Hz
100E+03100E+061E+06
THD – dB
10E+06
–20
Figure 8.THD vs. Clock Frequency
TEMPERATURE – °C
REF
– V
1.000406080
Figure 9.Voltage Reference Error vs. Temperature
CLOCK FREQUENCY – MHz
POWER CONSUMPTION – mW
CLOCK FREQUENCY – MHz
POWER CONSUMPTION – mW
78.081012141618
Figure 10.Power Consumption vs. Clock Frequency
(MODE = AVSS)
900k
N–1N
HITS
N+1
800k
700k
100k
400k
300k
200k
CODE
600k
500k
Figure 11.Grounded Input Histogram
SINGLE TONE FREQUENCY DOMAIN
0E+010E+61E+62E+63E+64E+65E+66E+67E+68E+69E+6
–80
Figure 12.Single-Tone Frequency Domain
AD9200
Table I.Mode Selection
External Ref
1.0E+61.0E+910.0E+6
SIGNAL AMPLITUDE – dB
100.0E+6
FREQUENCY – Hz
–27
Figure 13.Full Power Bandwidth
INPUT VOLTAGE – V
–
Figure 14.Input Bias Current vs. Input Voltage
APPLYING THE AD9200
THEORY OF OPERATION
The AD9200 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9200 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9200 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The AD9200 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876 A/D.
To realize this flexibility, internal switches on the AD9200 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as the Table I should
assist in picking the desired mode.
SUMMARY OF MODES
VOLTAGE REFERENCE
1 V Mode the internal reference may be set to 1 V by connect-
ing REFSENSE and VREF together.
2 V Mode the internal reference my be set to 2 V by connecting
REFSENSE to analog ground
External Divider Mode the internal reference may be set to a
point between 1 V and 2 V by adding external resistors. See
Figure 16f.
External Reference Mode enables the user to apply an exter-
nal reference to REFTS, REFBS and VREF pins. This mode
is attained by tying REFSENSE to VDD.
REFERENCE BUFFER
Center Span Mode midscale is set by shorting REFTS and
REFBS together and applying the midscale voltage to that point
The MODE pin is set to AVDD/2. The analog input will swing
about that midscale point.
Top/Bottom Mode sets the input range between two points.
The two points are between 1V and 2V apart. The Top/Bottom
Mode is enabled by tying the MODE pin to AVDD.
ANALOG INPUT
Differential Mode is attained by driving the AIN pin as one
differential input and shorting REFTS and REFBS together and
driving them as the second differential input. The MODE pin
is tied to AVDD/2. Preferred mode for optimal distortion
performance.
Single-Ended is attained by driving the AIN pin while the
REFTS and REFBS pins are held at dc points. The MODE pin is
tied to AVDD.
Single-Ended/Clamped (AC Coupled) the input may be
clamped to some dc level by ac coupling the input. This is done
by tying the CLAMPIN to some dc point and applying a pulse
to the CLAMP pin. MODE pin is tied to AVDD.
SPECIAL
AD876 Mode enables users of the AD876 to drop the AD9200
into their socket. This mode is attained by floating or grounding
the MODE pin.
INPUT AND REFERENCE OVERVIEW
Figure 16, a simplified model of the AD9200, highlights the
relationship between the analog input, AIN, and the reference
voltages, REFTS, REFBS and VREF. Like the voltages applied
to the resistor ladder in a flash A/D converter, REFTS and
REFBS define the maximum and minimum input voltages to
the A/D.
The input stage is normally configured for single-ended opera-
tion, but allows for differential operation by shorting REFTS
and REFBS together to be used as the second input.AIN
REFTS
REFBS
Figure 15.AD9200 Equivalent Functional Input Circuit
In single-ended operation, the input spans the range,
REFBS £ AIN £ REFTS
where REFBS can be connected to GND and REFTS con-
nected to VREF. If the user requires a different reference range,
REFBS and REFTS can be driven to any voltage within the
power supply rails, so long as the difference between the two is
between 1 V and 2 V.
In differential operation, REFTS and REFBS are shorted to-
gether, and the input span is set by VREF,
(REFTS – VREF/2) £ AIN £ (REFTS + VREF/2)
where VREF is determined by the internal reference or brought
in externally by the user.
The best noise performance may be obtained by operating the
AD9200 with a 2 V input range. The best distortion perfor-
mance may be obtained by operating the AD9200 with a 1 V
input range.
REFERENCE OPERATION
The AD9200 can be configured in a variety of reference topolo-
gies. The simplest configuration is to use the AD9200’s onboard
bandgap reference, which provides a pin-strappable option to
generate either a 1 V or 2 V output. If the user desires a refer-
ence voltage other than those two, an external resistor divider
can be connected between VREF, REFSENSE and analog
ground to generate a potential anywhere between 1 V and 2 V.
Another alternative is to use an external reference for designs
requiring enhanced accuracy and/or drift performance. A
third alternative is to bring in top and bottom references,
bypassing VREF altogether.
Figures 16d, 16e and 16f illustrate the reference and input ar-
chitecture of the AD9200. In tailoring a desired arrangement,
the user can select an input configuration to match drive circuit.
Then, moving to the reference modes at the bottom of the
figure, select a reference circuit to accommodate the offset and
amplitude of a full-scale signal.
Table I outlines pin configurations to match user requirements.
AD9200
AIN
+F/S RANGE OBTAINED
FROM VREF PIN OR
EXTERNAL REF
–F/S RANGE OBTAINED
FROM VREF PIN OR
EXTERNAL REF
+FS
–FSTop/Bottom ModeDifferential Mode1 V Reference2 V ReferenceVariable ReferenceInternal Reference Disable
MIDSCALE OFFSET
VOLTAGE IS DERIVED
FROM INTERNAL OR
EXTERNAL REF
MIDSCALE
* MAXIMUM MAGNITUDE OF V IS DETERMINED
BY INTERNAL REFERENCE
REFTS
REFBS
AINCenter Span Mode
The actual reference voltages used by the internal circuitry of
the AD9200 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
Figure 17. Reference Decoupling Network
Note:REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
REFBS = reference bottom, sense
INTERNAL REFERENCE OPERATION
Figures 18, 19 and 20 show example hookups of the AD9200
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9200
for 1V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0 mF tantalum capacitor in
parallel with a low inductance, low ESR, 0.1 mF ceramic capacitor.
Figure 18.Internal Reference 1 V p-p Input Span
(Top/Bottom Mode)
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
Figure 19.Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
Figure 20.Internal Reference 1 V p-p Input Span,
(Center Span Mode)
AD9200
EXTERNAL REFERENCE OPERATION
Using an external reference may provide more flexibility and
improve drift and accuracy. Figures 21 through 23 show ex-
amples of how to use an external reference with the AD9200.
To use an external reference, the user must disable the internal
reference amplifier by connecting the REFSENSE pin to VDD.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins.
The AD9200 contains an internal reference buffer (A2), that
simplifies the drive requirements of an external reference. The
external reference must simply be able to drive a 10 kW load.
Figure 21 shows an example of the user driving the top and bottom
references. REFTS is connected to a low impedance 2 V source
and REFBS is connected to a low impedance 1 V source. REFTS
and REFBS may be driven to any voltage within the supply as
long as the difference between them is between 1 V and 2 V.
Figure 21.External Reference Mode—1 V p-p Input Span
Figure 22 shows an example of an external reference generating
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10kW, capacitive load. Choose
this op amp based on noise and accuracy requirements.
Figure 22.External Reference Mode—1 V p-p Input
Span 2.5 VCM
Figure 23a shows an example of the external references driving
the REFTF and REFBF pins that is compatible with the
AVDD
Figure 23a.External Reference—2 V p-p Input Span
REFT
REFB
Figure 23b.Kelvin Connected Reference Using the AD9200
STANDBY OPERATION
The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
holding the clock at logic low. In this mode the typical power
drain is approximately 4 mW. If there is no connection to the
STBY pin, an internal pull-down circuit will keep the ADC in a
“wake-up” mode of operation.
The ADC will “wake up” in 400 ns (typ) after the standby pulse
goes low.
CLAMP OPERATION
The AD9200ARS and AD9200KST parts feature an optional
clamp circuit for dc restoration of video or ac coupled signals.
Figure 24 shows the internal clamp circuitry and the external
control signals needed for clamp operation. To enable the
clamp, apply a logic high to the CLAMP pin. This will close
the switch SW1. The clamp amplifier will then servo the volt-
age at the AIN pin to be equal to the clamp voltage applied at
the CLAMPIN pin. After the desired clamp level is attained,
SW1 is opened by taking CLAMP back to a logic low. Ignoring
the droop caused by the input bias current, the input capacitor
CIN will hold the dc voltage at AIN constant until the next
clamp interval. The input resistor RIN has a minimum recom-
mended value of 10W, to maintain the closed-loop stability of
the clamp amplifier.
The allowable voltage range that can be applied to CLAMPIN
depends on the operational limits of the internal clamp ampli-

Partno	Mfg	Dc	Qty	Available	Descript
AD9200ARS		N/a	11	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
AD9200JRS	ADI	N/a	12	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
AD9200JRS	AD	N/a	52	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
AD9200JST	ADI	N/a	1	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
AD9200JSTRL	AD	N/a	1164	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
AD9200KST	AD ?	N/a	38	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
AD9200KSTRL	AD	N/a	185	avai	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter