AD9100AD-AD9100JD Fast Delivery |IC PHOENIX CO.,LIMITED

AD9100AD ,Ultrahigh Speed Monolithic Track-and-HoldSpecifications subject to change without notice.–2– REV. BAD9100APERTURE+2VDELAY(0.8ns)ANALOG0VINPU ..
AD9100JD ,Ultrahigh Speed Monolithic Track-and-HoldCHARACTERISTICSS S LOAD IN1Test AD9100JD/AD/SDParameter Conditions Temp Level Min Typ Max Units ..
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AD9100AD-AD9100JD
Ultrahigh Speed Monolithic Track-and-Hold
FUNCTIONAL BLOCK DIAGRAM
REV.BUltrahigh Speed
Monolithic Track-and-Hold
FEATURES
Excellent Hold Mode Distortion into 250 V
–88 dB @ 30 MSPS (2.3 MHz VIN)
–83 dB @ 30 MSPS (12.1 MHz VIN)
–74 dB @ 30 MSPS (19.7 MHz VIN)
16 ns Acquisition Time to 0.01%
<1 ps Aperture Jitter
250 MHz Tracking Bandwidth
83 dB Feedthrough Rejection @ 20 MHz
3.3 nV/√Hz Spectral Noise Density
MlL-STD-Compliant Versions Available
APPLICATIONS
A/D Conversion
Direct IF Sampling
Imaging/FLIR Systems
Peak Detectors
Radar/EW/ECM
Spectrum Analysis
CCD ATE
GENERAL DESCRIPTION
The AD9100 is a monolithic track-and-hold amplifier which
sets a new standard for high speed and high dynamic range
applications. It is fabricated in a mature high speed complemen-
tary bipolar process. In addition to innovative design topologies,
a custom package is utilized to minimize parasitics and optimize
dynamic performance.
Acquisition time (hold to track) is 13 ns to 0.1% accuracy, and
16 ns to 0.01%. The AD9100 boasts superlative hold-mode
frequency domain performance; when sampling at 30 MSPS
hold mode distortion is less than 83 dBfs for analog frequencies
up to 12 MHz; and –74 dBfs at 20 MHz. The AD9100 can also
drive capacitive loads up to 100 pF with little degradation in
acquisition time; it is therefore well suited to drive 8- and 10-bit
flash converters at clock speeds to 50 MSPS. With a spectral
noise density of 3.3 nV/√Hz and feedthrough rejection of 83 dB
at 20 MHz, the AD9100 is well suited to enhance the dynamic
range of many 8- to 16-bit systems.
The AD9100 is “user friendly” and easy to apply: (1) it requires
+5 V/–5.2 V power supplies; (2) the hold capacitor and switch
power supply decoupling capacitors are built into the DIP pack-
age; (3) the encode clock is differential ECL to minimize clock
jitter; (4) the input resistance is typically 800 kΩ; (5) the analog
input is internally clamped to prevent damage from voltage
transients.
The AD9100 is available in a 20-lead side-brazed “skinny DIP”
package. Commercial, industrial, and military temperature
grade parts are available. Consult the factory for information
about the availability of 883-qualified devices.
PRODUCT HIGHLIGHTSHold Mode Distortion is guaranteed.Monolithic construction.Analog input is internally clamped to protect against over-
voltage transients and ensure fast recovery.Output is short circuit protected.Drives capacitive loads to 100 pF.Differential ECL clock inputs.
*Patent pending.
AD9100–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
CLOCK/CLOCK INPUTS
TRACK MODE DYNAMICS
HOLD MODE DYNAMICS
NOTESAD9100JD: 0°C to +70°C. AD9100AD: –40°C to +85°C. AD9100SD: –55°C to +125°C. DIP θJA = 38°C/W; this is valid with the device mounted flush to a
grounded 2 oz. copper clad board with 16 sq. inches of surface area and no air flow.
(unless otherwise noted, +VS = +5 V; –VS = –5.2 V; RLOAD = 100 V; RIN = 50 V)
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures.
III–Periodically sample tested.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9100 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
EVALUATION BOARD ORDERING INFORMATION
CLOCK
INPUTS
+2V
–2V
ANALOG
INPUT
+2V
–2V
"1"
"0"
HOLD CAPACITOR/
ANALOG OUTPUT
Figure 1.Timing Diagram (1 ns/div)
ABSOLUTE MAXIMUM RATINGS1
Supply Voltages (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . .±6 V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . .70 mA
Analog Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . .±5 V
Operating Temperature Range (Case)
AD9100JD . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
AD9100AD . . . . . . . . . . . . . . . . . . . . . . . . .–25°C to +85°C
AD9100SD . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Analog input voltage should not exceed ±VS.
AD9100
PIN FUNCTION DESCRIPTIONS/CONNECTIONS
CHIP PAD ASSIGNMENTS
GNDNC
CLOCK
HOLD CAP
(NOTE 3)
+VS CAP
(NOTE 1)
CLOCK
GND
BYPASS
(NOTE 2)
+VS+VS+VS+VS+VS
BYPASS
(NOTE 2)
–VS–VIN–VS–VS CAP
(NOTE 1)
–VS
SIZE = 148 3 63 3 15 milsNC = NO CONNECT
NOTES:
1. SUPPLY BYPASS CAPACITOR; 0.01 TO 0.1mF CERAMIC
CONNECTED TO GROUND.
2. 0.01mF CERAMIC CONNECTED BETWEEN PAD 29 AND PAD 31.
3. HOLD CAPACITOR CONNECTED FROM PAD 4 AND PAD 5 TO
GROUND; 10–100pF, NOMINALLY 22pF. DIP PACKAGE DOES NOT
REQUIRE EXTERNAL HOLD CAPACITOR.
BYPASS
–VS
GND
+VS
CLK
–VS
–VS
+VS
BYPASS
+VS
GND
VIN
CLK
GND
GNDGND
VOUTGND
GNDGND
PIN CONFIGURATION
20-Lead Side-Brazed Ceramic DIP
TERMINOLOGY
Analog Delay is the time required for an analog input signal to
propagate from the device input to output.
Aperture Delay tells when the input signal is actually sampled.
It is the time difference between the analog propagation delay of
the front-end buffer and the control switch delay time. (The
time from the hold command transition to when the switch is
opened.) For the AD9100, this is a positive value which means
that the switch delay is longer than the analog delay.
Aperture Jitter is the random variation in the aperture delay.
This is measured in ps-rms and results in phase noise on the
held signal.
Droop Rate is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9100 output with the
device in hold mode and the input held at a specified dc value,
the measurement starts immediately after the T/H switches from
track to hold. Feedthrough Rejection is the ratio of the input
signal to the output signal when in hold mode. This is a mea-
sure of how well the switch isolates the input signal from feeding
through to the output.
Hold-to-Track Switch Delay is the time delay from the track
command to the point when the output starts to change and
acquire a new signal.
Pedestal Offset is the offset voltage step measured immediately
after the AD9100 is switched from track to hold with the input
held at zero volts. It manifests itself as an added offset during
the hold time.
Track-to-Hold Settling Time is the time necessary for the
track to hold switching transient to settle to within 1 mV of its
final value.
Track-to-Hold Switching Transient is the maximum peak
switch induced transient voltage which appears at the AD9100
output when it is switched from track to hold.
Figure 4.Recommended RS vs. CLOAD
for Optimal Settling Times
100ns/DIV
2mV/DIV
Figure 7.Track-to-Hold-to-Track Switch
Transients2010
INPUT FREQUENCY – MHz
SNR, INCLUDING HARMONICS – dB
Figure 10.SNR vs. Analog Input
INPUT FREQUENCY – MHz
PSRR – dB
Figure 3.Power Supply Rejection
Ratio vs. Frequency+125
+25
+750
mV/
TEMPERATURE – 8C
Figure 6.Magnitude of Droop Rate
vs. Temperature
AD9100
AIN
THE AD9060 IS A 10-BIT, 75MSPS MONOLITHIC
ADC FROM ANALOG DEVICES.
*THE AD9100XD (DIP) HAS AN INTERNAL 22pF
HOLD CAPACITOR.
Figure 9.
% OF FULL SCALE
30060DC240180120
INPUT FREQUENCY – MHz
GAIN – dB
Figure 2.Gain vs. Frequency (Track
Mode)
INPUT FREQUENCY – MHz
dBc
Figure 5.Worst Hold Mode Harmonic
vs. Analog Input Frequency402030
INPUT FREQUENCY – MHz
SNR, INCLUDING HARMONICS – dB
Figure 8.SNR vs. Analog Input
105
AD9100
Acquisition Time
Acquisition time is the amount of time it takes the AD9100 to
reacquire the analog input when switching from hold to track
mode. The interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
The hold to track switch delay (tDHt) cannot be subtracted
from this acquisition time because it is a charging time delay
that occurs when moving from hold to track; this is typicallyns to 6 ns and is the longest delay. Therefore, the track time
required for the AD9100 is the acquisition time minus the aper-
ture delay time. Note that the acquisition time is defined as the
settled voltage at the hold capacitor and does not include the
delay and settling time of the output buffer. The example below
illustrates why the output buffer amplifier does not contribute to
the overall AD9100 acquisition time.
VOUTVIN
TIME
PEAK TRANSIENT
SEEN BY OUTPUT
BUFFER
tDHT
6ns
VCH
VOUT
ACQUISITION TIME AT
CH TO X%
Figure 13.Acquisition Time Diagram
The exaggerated illustration in Figure 13 shows that VCH has
settled to within x% of its final value, but VOUT (due to slew rate
limitations, finite BW, power supply ringing, etc.) has not
settled during the track time. However, since the output buffer
always “tracks” the front end circuitry, it “catches up” during
the hold time and directly superimposes itself (less about 600 ps
of analog delay) to VCH. Since the small-signal settling time of
the output buffer is about 1.8 ns to ±1 mV and is significantly
less than the specified hold time, acquisition time should be
referenced to the hold capacitor.
Note that most of the hold settling time and output acquisition
time are due to the input buffer and the switch network. For
track time, the output buffer contributes only about 5 ns of the
total; in hold mode, it contributes only 1.8 ns (as stated above).
A stricter definition of acquisition time would total the acquisi-
tion and hold times to a defined accuracy. To obtain 12 bit +
distortion levels and 30 MSPS operation, the recommended
track and hold times are 20 ns and 13.5 ns, respectively. To
drive an 8-bit flash converter with a 2 V p-p full-scale input,
hold time to 1 LSB accuracy will be limited primarily by the
THEORY OF OPERATION
The AD9100 utilizes a new track and hold architecture. Previ-
ous commercially available high speed track and holds used an
open loop input buffer, followed by a diode bridge, hold capaci-
tor, and output buffer (closed or open loop) with a FET device
connected to the hold capacitor. This architecture required
mixed device technology and, usually, hybrid construction. The
sampling rate of these hybrids has been limited to 20 MSPS for
12-bit accuracy. Distortion generated in the front-end amplifier/
bridge limited the dynamic range performance to the “mid-70
dBfs” for analog input signals of less than 10 MHz. Broadband
and switch-generated noise limited the SNR of previous track
and holds to about 70 dB.
The AD9100 is a monolithic device using a high frequency
complementary bipolar process to achieve new levels of high
speed precision. Its patent pending architecture breaks from the
traditional architecture described above. (See the block diagram
on the first page.) The switching type bridge has been integrated
into the first stage closed loop input amplifier. This innovation
provides error (distortion) correction for both the switch and
amplifier, while still achieving slew rates representative of an
open-loop design. In addition, acquisition slew current for the
hold capacitor is higher than standard diode bridge and switch
configurations, removing a main contributor to the limits of
maximum sampling rate and input frequency.
Switching circuits in the device use current steering (versus
voltage switching) to provide improved isolation between the
switch and analog sections. This results in low aperture time
sensitivity to the analog input signal, and reduced power supply
and analog switching noise. Track to hold peak switching tran-
sient is typically only 6 mV and settles to less than 1 mV in 7 ns.
In addition, pedestal sensitivity to analog input voltage is very
low (0.6 mV/V) and being first order linear does not significantly
affect distortion.
The closed-loop output buffer includes zero voltage bias current
cancellation, which results in high-temperature droop rates
equivalent to those found in FET type inputs. The buffer also
provides first order quasistatic bias correction resulting in an
extremely high input resistance and very low droop sensitivity vs.
input voltage level (typically less than 1.5 mV/V–μs.) This
closed-loop architecture inherently provides high speed loop
correction and results in low distortion under heavy loads.
The extremely fast time constant linearity (7 ns to 0.01% for a
2 V step) ensures that the output buffer does not limit the
AD9100 sampling rate or analog input frequency. (The acquisi-
tion and settling time are primarily limited only by the input
amplifier and switch.) The output is transparent to the overall
AD9100 hold mode distortion levels for loads as low as 250 Ω.
Full-scale track and acquisition slew rates achieved by the
AD9100 are 800 and 1000 V/μs, respectively. When combined
with excellent phase margin (typically 5% overshoot), wide
bandwidth, and dc gain accuracy, acquisition time to 0.01% is
only 16 ns. Though not production tested, settling to 14-bit
accuracy (–86 dB distortion @ 2.3 MHz) can be inferred to be
20 ns.

Partno	Mfg	Dc	Qty	Available	Descript
AD9100AD	AD	N/a	5	avai	Ultrahigh Speed Monolithic Track-and-Hold
AD9100JD	AD	N/a	2	avai	Ultrahigh Speed Monolithic Track-and-Hold