AD9066AR-REEL ,Dual, 6-Bit, 60 MSPS Monlithic A/D ConverterSpecifications subject to change without notice.–2– REV. AAD9066PIN DESCRIPTIONSABSOLUTE MAXIMUM RA ..
AD9066ARS ,Dual 6-Bit, 60 MSPS Monolithic A/D Converterapplications, the midscale voltageINB 4 25GNDreference can be used to control external biasing ampl ..
AD9066JR ,Dual 6-Bit, 60 MSPS Monolithic A/D ConverterSpecifications subject to change without notice.–2– REV. AAD9066PIN DESCRIPTIONSABSOLUTE MAXIMUM RA ..
AD9071BR ,10-Bit, 100 MSPS A/D ConverterSPECIFICATIONSTest AD9071BRParameter Temp Level Min Typ Max UnitsRESOLUTION 10 BitsDC A ..
AD9100AD ,Ultrahigh Speed Monolithic Track-and-HoldSpecifications subject to change without notice.–2– REV. BAD9100APERTURE+2VDELAY(0.8ns)ANALOG0VINPU ..
AD9100JD ,Ultrahigh Speed Monolithic Track-and-HoldCHARACTERISTICSS S LOAD IN1Test AD9100JD/AD/SDParameter Conditions Temp Level Min Typ Max Units ..
ADS6122IRHBT ,Low Power 12-bit 65MSPS ADC with selectable parallel CMOS or LVDS outputs 32-VQFN -40 to 85features• No External Decoupling Required forexist to ease data capture such as — controls forRefer ..
ADS6123IRHBT ,Low Power 12-bit 80MSPS ADC with selectable parallel CMOS or LVDS outputs 32-VQFN -40 to 85SLAS560A–OCTOBER 2007–REVISED MARCH 2008This integrated circuit can be damaged by ESD. Texas Instru ..
ADS6124IRHBT ,Low Power 12-bit 105MSPS ADC with selectable parallel CMOS or LVDS outputs 32-VQFN -40 to 85features• No External Decoupling Required forexist to ease data capture such as — controls forRefer ..
ADS6145IRHBT ,Low Power 14-bit 125MSPS ADC with selectable parallel CMOS or LVDS outputs 32-VQFN -40 to 85features• No External Decoupling Required forexist to ease data capture such as — controls forRefer ..
ADS6148IRGZR ,Low power 14-bit, 210 MSPS ADC 48-VQFN -40 to 85FEATURESDESCRIPTION• Maximum Sample Rate: 250 MSPS• 14-Bit Resolution – ADS614XADS614X (ADS612X) is ..
ADS6148IRGZT ,Low power 14-bit, 210 MSPS ADC 48-VQFN -40 to 85(1)(2)PACKAGE/ORDERING INFORMATIONSPECIFIEDPACKAGE LEAD/BALL PACKAGE ORDERING TRANSPORTPRODUCT PACK ..
AD9066AR-REEL
Dual, 6-Bit, 60 MSPS Monlithic A/D Converter
FUNCTIONAL BLOCK DIAGRAMREV.A
Dual 6-Bit, 60 MSPS
Monolithic A/D Converter
PRODUCT DESCRIPTIONThe AD9066 is a dual 6-bit ADC that has been optimized for
low-cost in-phase and quadrature (I and Q) demodulators.
Primary applications include digital direct broadcast satellite
applications where broadband quadrature phase shift keying
(QPSK) modulation is used. In these receivers the recovered signal
is separated into I and Q vector components and digitized.
To reduce total system cost and power dissipation, the AD9066
provides an internal voltage reference and operates from a
single +5 volt power supply.Digital outputs are CMOS com-
patible and rated to 60 MSPS conversion rates. The digital
input (ENCODE) utilizes a CMOS input stage with a TTL
compatible (1.4V) threshold.
The AD9066 is housed in a 28-lead SOIC and a 28-lead SSOP
package and is available in two temperature grades. The
AD9066JR is rated for operation over the 0°C to 70°C commer-
cial temperature range.The AD9066AR/ARS is rated for the
–40°C to +85°C industrial temperature range.
The internal voltage reference insures that the analog input is
biased to midscale with low offset when driven from an ac-
coupled source. In dc-coupled applications, the midscale voltage
reference can be used to control external biasing amplifiers to
minimize offsets due to variations in temperature or supply voltage.
FEATURES
Two Matched ADCs on Single Chip
CMOS-Compatible I/O
Low-Power (400 mW) Dissipation
Single +5 V Supply
On-Chip Voltage Reference
Self-Biased for AC-Coupled Inputs
28-Lead SOIC and SSOP Packages
APPLICATIONS
Direct Broadcast Satellite (DBS) Receivers
QAM Demodulators
Wireless LANs
VSAT Receivers
PIN CONFIGURATIONS
ELECTRICAL CHARACTERISTICSENCODE INPUT
NOTESFor ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For
dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset.
Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage.tV and tPD are measured from the 1.4V level of the Clock and the 50% level between VOHand VOL. The ac load on all the digital outputs during test is 10 pF (max),
the dc load will not exceed ±40µA. Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by
ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input.Typical thermal impedance for the “R” style (SOIC) 28-lead package is: θJC = 4°C/W, θCA = 41°C/W, θJA = 45°C/W, and the “RS” style (SSOP) 28-lead package is:
θJC = 26.97°C/W, θCA = 51.61°C/W, θJA = 78.58°C/W.
Specifications subject to change without notice.
AD9066–SPECIFICATIONS
(+VS = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, TC = TA)
ABSOLUTE MAXIMUM RATINGSINA, INB
EXPLANATION OF TEST LEVELS
PIN DESCRIPTIONS
DIE LAYOUT AND MECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . . . . 132 × 68 × 21 (±1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,810
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9066 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*R = “SO” Small Outline Package; RS = SSOP.
MHz
ENOB – Bits
5.2100Figure 1.ENOB vs. Analog Input Frequency
MHz
ENOB
Bits
5.2100Figure 2.ENOB vs. Encode Rate
USING THE AD9066
Analog Input and Voltage ReferencesThe AD9066 is optimized to allow ac coupled inputs with a full-
scale input range of 500 mV ± 5%. An LSB weight is approxi-
mately 8 mV. The full-scale input range is defined as the voltage
range that accommodates 2n – 2 codes of equally weighted LSBs
(between the first and last code transitions). For the AD9066
there are 32 codes above and below the midscale voltage of thesee Figure 3).
The full-scale input range of the AD9066 is equal to 500/620 ×
(VT – VB), or nominally 500 mV. For dc coupled applications,
the REFAand REF B voltages can be used to feed back offset
compensation signals. This will allow the midscale transition
voltage of the ADCs to track supply and temperature variations.
In the event that offset correction signals are generated digitally,
the REF pins would not be required. Figure 4a shows the
equivalent circuit for the internal references. All component
tolerances are ±25%.
Gain VariationThe full-scale input range is established by the current through
the two matched resistor ladders (620 ohms each nominal). There-
fore the gain of the ADC may be modified by forcing different
voltages across the top and bottom voltage taps (VT and VB).
The easiest way to increase the input range will be to force VB
to a lower voltage. Using an external amplifier, the voltage at VB
may be forced as low as 3.0 V (3.58 nominal). Using the pre-
viously described relationship for full scale and the internal
resistor ladder values, 3.0 V at VB will result in a nominal full-
scale input range of 705 mV.
A larger input range can be established by taking the VT voltage
all the way to the supply voltage level while pulling VB to 3.0 V.
This would force a 2 V potential across the ladder and create a
full-scale input range of 1.6 V.
Greater flexibility and improved power supply rejection can be
achieved by forcing external voltage references at both the top
and bottom of the resistor ladder.
Figure 3.
Figure 4.Equivalent Circuits
d. Analog Inputc. Output Bits
AD9066
TimingThe duty cycle of the encode clock for the AD9066 is critical in
obtaining rated performance of the ADC. Rated maximum and
minimum pulse widths should be maintained, especially for
sample rates greater than 40 MSPS.
The AD9066 provides latched data outputs with three pipeline
delays. The length and load on the output data lines should be
minimized to reduce power supply transients inside the AD9066
which might diminish dynamic performance.
Figure 5.Timing Diagram
The data is invalid during the period between tV and tPD. This
period refers to the time required for the AD9066 to fully switch
between valid CMOS logic levels. When latching the output
data, be careful to observe latch setup and hold time restrictions
as well as this data invalid period when designing the system
timing.
Layout and Signal CareTo insure optimum performance, a single low impedance
ground plane is recommended. Analog and digital grounds
should be connected together at the AD9066. Analog and digi-
tal power supplies should be bypassed, at the device, to ground
through 0.1µF ceramic capacitors.
The use of sockets may limit the dynamic performance of the
part and is not recommended except for prototype or evaluation
purposes.
Driving the AD9066 with a Bipolar InputThe analog input range of the AD9066 is between 3.7 V and
4.2V. Because the input is offset, the normal method of driving
the analog input is to use a blocking capacitor between the ana-
log source and the AD9066 analog input pins. In applications
where DC coupling must be employed, the simple circuit shown
in Figure 6 will take a bipolar input and offset it to the operating
range of the AD9066.
To offset the input, the midpoint voltage of the AD9066 is buff-
ered off chip and then inverted with an AD712, a low input bias
current dual op amp. This inverted midpoint is then fed to a
summation amplifier that combines the bipolar input with the
inverted offset voltage. The summation amplifier is an AD812, a
wideband current feedback amplifier that provides good band-
width and low distortion.
Figure 6.Bipolar Input Using AD812 Drive for AD9066
Layout should follow high frequency/high speed design guide-
lines. In addition the capacitance around the inverting input to
the AD812 should be minimized through a tight layout and the
use of low capacitance chip resistors for gain setting.
Quadrature Receiver Using the AD9066Although any type of input signal may be applied, the AD9066
has been optimized for low cost in-phase and quadrature (I and
Q) demodulators. Primary applications include digital direct
broadcast satellite applications where broadband quadrature
phase shift keying (QPSK) modulation is used. In these receivers
the recovered signal is separated into I and Q vector components
and digitized.
Figure 7.Simplified Block Diagram
For data symbol rates less than 10 Mbaud, the AD607 IF/RF
receiver subsystem provides an ideal solution for the second
conversion stage of a complete receiver system. Figure 8 shows
the AD9066 and AD607 used together.
The AD607 accepts inputs as high as 500 MHz which may be
the output of the first IF stage or RF signals directly. The IF/RF
signal is mixed with the local oscillator to provide an IF fre-
quency of 400 kHz to 22 MHz. This signal is filtered externally
and then amplified with an on-chip AGC before being synchro-
nously demodulated with an on-chip PLL carrier recovery
circuit. The outputs are digitized with the AD9066. The digital
outputs may be processed with a DSP chip such as the ADSP-
2171, ADSP-21062, general purpose DSP or ASIC.
Figure 8.Digitizer with AD607 Receiver Circuit
Theory of OperationThe AD9066 dual ADC employs a patented interpolated flash
architecture. This architecture enables 64 possible quantization
levels with only 32 comparator preamplifiers. This keeps input
capacitance to a minimum. The midpoint of the reference lad-
der is fed back to the analog input, allowing easy biasing of the
ADC to midscale for ac coupled applications.
As shown in Figure 4d, a simple resistor is used to provide the
reference ladder midpoint to the analog input. The high imped-
ance MOS inputs of the comparators insure no static voltage
drop across the resistor. This eliminates the need for an active
buffer (and its inherent offsets) to set the reference midpoint at
the analog input.
The outputs of the comparators are converted to a 6-bit word
and converted to CMOS levels. The digital signals are latched at
six stages (two pipeline delays) in the signal path. The digital
outputs are CMOS with approximately equal rise and fall times.
The encode clock utilizes a CMOS input stage with TTL-
compatible (1.4 V) thresholds. Internal clock buffers minimize
external clock drive requirements.
AD9066
