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ADS58H40IZCR ,Quad 250MSPS Receiver and Feedback IC 144-NFBGA -40 to 85 SBAS589B –AUGUST 2012–REVISED NOVEMBER 2012THERMAL INFORMATIONADS58H40(1)THERMAL METRIC ZCR (BGA) ..
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AD9060JE-AD9060JZ-AD9060KE-AD9060KZ
10-Bit 75 MSPS A/D Converter
REV.A
10-Bit 75 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAMENCODE
ANALOG IN
GROUND
OVERFLOW
LSBS
INVERT
MSB
INVERTENCODE
+VREF
+VSENSE
–VREF
–VSENSE
3/4REF
1/2REF
1/4REF
–VS+VS
D9 (MSB)
D0 (LSB)
FEATURES
Monolithic 10-Bit/75 MSPS Converter
ECL Outputs
Bipolar (61.75 V) Analog Input
57 dB SNR @ 2.3 MHz Input
Low (45 pF) Input Capacitance
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems
GENERAL DESCRIPTIONThe AD9060 A/D converter is a 10-bit monolithic converter ca-
pable of word rates of 75 MSPS and above. Innovative architec-
ture using 512 input comparators instead of the traditional 1024
required by other flash converters reduces input capacitance and
improves linearity.
Inputs and outputs are ECL-compatible, which makes the
AD9060 the recommended choice for systems with conversion
rates >30 MSPS to minimize system noise. An overflow bit is
provided to indicate analog input signals greater than +VSENSE.
Voltage sense lines are provided to ensure accurate driving of
the ±VREF voltages applied to the units. Quarter-point taps on
the resistor ladder help optimize the integral linearity of the
unit.
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and specifically designed for low thermal im-
pedances. Two performance grades for temperatures of both
0°C to +70°C and –55°C to +125°C ranges are offered to allow
the user to select the linearity best suited for each application.
Dynamic performance is fully characterized and production
tested at +25°C. MIL-STD-883 units are available.
The AD9060 A/D converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9060/883B data sheet for detailed
specifications.
AD9060–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . .–2 V to +2 V
+VREF, –VREF, 3/4REF, 1/2REF, 1/4REF . . . . . . . . . –2 V to +2 V
+VREF to –VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0 V
ENCODE, ENCODE . . . . . . . . . . . . . . . . . . . . . . .0 V to –VS
3/4REF, 1/2REF, 1/4REF Current . . . . . . . . . . . . . . . . . .±10 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature
AD9060JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . .+175°C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . .+300°C
ELECTRICAL CHARACTERISTICS
(+VS = +5 V; –VS = –5.2 V; 6VSENSE = 61.75 V; ENCODE = 60 MSPS
unless otherwise noted)3
AD9060DIGITAL OUTPUTS
POWER SUPPLY
NOTES
1Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W
(air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM).
33/4REF, 1/2REF and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V and –0.875 V, respectively. Outputs terminated through 100 Ω to –2.0 V;
CL < 4 pF. Accuracy of the overflow comparator is not tested and not included in linearity specifications.
4Measured with ANALOG IN = +VSENSE
5Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D0–D9. Output skew
measured as worst-case difference in output delay among D0–D9.
6RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
7Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change m +VS or –VS.
Specifications subject to change without notice.
AD9060
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C and sample tested at
specified temperatures.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes
for commercial/industrial devices.
DIE LAYOUT AND MECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . . .206 × 140 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9060 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDEAD9060JE
AD9060KZ
AD9060KE
AD9060SZ
NOTESE = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.For specifications, refer to Analog Devices Military Products Databook.
AD9060 PIN DESCRIPTIONS27
AD9060
TOP VIEW
(Not to scale)
ENCODE
GND
(LSB) D04NC
ANALOG INANALOG INGNDGND1/4
REFGNDGNDMSB INVERT
LSBs INVERT
GND
OVERFLOW
D9 (MSB)
GNDGNDGNDGNDGNDGNDGND
ENCODE
GND
GNDGND
GND1685
1/2
REF
3/4
REF
+VSENSESENSEREFREFSSSAD9060 Pin Designations
AD9060
MIL-STD-883 Compliance InformationThe AD9060 devices are classified within Microcircuits Group
57, Technology Group D (bipolar A/D converters) and are con-
structed in accordance with MIL-STD-883. The AD9060 is
electrostatic sensitive and falls within electrostatic sensitivity
classification Class 1. Percent Defective Allowance (PDA) is
computed based on Subgroup 1 of the specified Group A test
list. Quality Assurance (QA) screening is in accordance with Al-
ternate Method A of Method 5005.
The following apply: Burn-In per 1015; Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes TA = TC = TJ.) MIL-STD-883-compliant devices are
marked with “C” to indicate compliance.
100W
41,42,54,64
0.1 mF
AD1
AD2
3,6,15,30,33,34,
STATIC:
DYNAMIC:
AD1 = –2V; AD 2 = ECL HIGH
AD3 = ECL LOW
AD1 = –2V TRIANGLE WAVE
AD2,AD3 = ECL PULSE TRAIN
+2V
–2V
5.0V+AD3
–5.2V 510W
510W
510W
510W
AD9060 Burn-ln Connections
THEORY OF OPERATIONRefer to the AD9060 block diagram. As shown, the AD9060
uses a modified “flash,” or parallel, A/D architecture. The ana-
log input range is determined by an external voltage reference
(+VREF and –VREF), nominally ±1.75 V. An internal resistor
ladder divides this reference into 512 steps, each representing
two quantization levels. Taps along the resistor ladder (1/4REF,
1/2REF and 3/4REF) are provided to optimize linearity. Rated
performance is achieved by driving these points at 1/4, 1/2 and
3/4, respectively, of the voltage reference range.
The A/D conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least signifi-
cant bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. The decoding logic processes
the comparator outputs and provides a 10-bit code to the out-
put stage of the converter.
Flash architecture has an advantage over other A/D architec-
tures because conversion occurs in one step. This means the
performance of the converter is limited primarily by the speed
and matching of the individual comparators. In the AD9060, an
innovative interpolation scheme takes advantage of flash archi-
tecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur because of using only half the normal
number of input comparator cells to accomplish the conversion.
In addition, a proprietary decoding scheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, Twos Complement and Inverted Twos
Complement coding (see AD9060 Truth Table).
APPLICATIONSMany of the specifications used to describe analog/digital con-
verters have evolved from system performance requirements in
these applications. Different systems emphasize particular speci-
fications, depending on how the part is used. The following ap-
plications highlight some of the specifications and features that
make the AD9060 attractive in these systems.
Wideband ReceiversRadar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence and
spectral analysis all place stringent ac performance requirements
on analog-to-digital converters (ADCs). Frequency domain
characterization of the AD9060 provides signal-to-noise ratio
(SNR) and harmonic distortion data to simplify selection of the
ADC.
Receiver sensitivity is limited by the Signal-to-Noise Ratio (SNR)
of the system. The SNR for an ADC is measured in the fre-
quency domain and calculated with a Fast Fourier Transform
(FFT). The SNR equals the ratio of the fundamental compo-
nent of the signal (rms amplitude) to the rms value of the
“noise.” The noise is the sum of all other spectral components,
including harmonic distortion but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the result
of imperfections in the device transfer function (nonlinearities,
delay mismatch, varying input impedance, etc.). In the ADC,
these spurious signals appear as Harmonic Distortion. Harmonic
Distortion is also measured with an FFT and is specified as the
ratio of the fundamental component of the signal (rms ampli-
