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ADS58B18IRGZR ,11 bit 200MSPS Buffered ADC with SNRBoost 48-VQFN -40 to 85features integrated analog buffers and• Integrated High-Impedance Analog InputSNRBoost technology. ..
ADS58B18IRGZT ,11 bit 200MSPS Buffered ADC with SNRBoost 48-VQFN -40 to 85MAXIMUM RATINGSADS58B18, ADS58B19MIN MAX UNITSupply voltage range, AVDD–0.3 2.1 VSupply voltage ran ..
AD9058JD-AD9058JJ-AD9058KJ-AD9058TJ/883
Dual 8-Bit 50 MSPS A/D Converter
REV.B
Dual 8-Bit 50 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
ENCODE
AIN
ENCODE
AIN
QUADRATURE RECEIVER
GENERAL DESCRIPTIONThe AD9058 combines two independent high performance
8-bit analog-to-digital converters (ADCs) on a single mono-
lithic IC. Combined with an optional onboard voltage refer-
ence, the AD9058 provides a cost effective alternative for
systems requiring two or more ADCs.
Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high per-
formance and low power (<0.5 watt/channel). Digital inputs
and outputs are TTL compatible.
Performance has been optimized for an analog input of 2 V
p-p (±1 V; 0 V to +2 V). Using the onboard +2 V voltage
reference, the AD9058 can be set up for unipolar positive
operation (0 V to +2 V). This internal voltage reference can
drive both ADCs.
Commercial (0°C to +70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.
FEATURES
Two Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1W)
Low Input Capacitance (10 pF)
65 V Power Supplies
Flexible Input Range
APPLICATIONS
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
Radar
AD9058–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1Analog Input . . . . . . . . . . . . . . . . . . . . . . . . .–1.5 V to +2.5 V
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.8 V to –6 V2
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . .53 mA
+VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.5 V
–VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–1.5
Operating Temperature Range
AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . .0°C to +70°C
Maximum Junction Temperature3
AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
ELECTRICAL CHARACTERISTICS
[�VS = �5 V; VREF = +2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to +2 V; –VREF =
GROUND, unless otherwise noted.]2 All specifications apply to either of the two ADCs
AD9058NOTESAbsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic DIP θJA = 40°C/W;
θJC = 12°C/W.To achieve guaranteed conversion rate, connect each data output to ground through a 2 kΩ pull-down resistor.SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
ORDERING GUIDENOTES
AD9058
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN DESCRIPTIONS28
GROUNDGROUND
REF
COMP
ENCODE
GROUNDGROUNDGROUND
NC
GROUND
(LSB)
–VS
–VREF
+VS
ENCODE
D7 (MSB)
NC = NO CONNECT
GROUND
–VS
–VREF
+VS
D7 (MSB)
0 (LSB)
INT
REFAD9058JJ/KJ Pinouts
D7 (MSB)
GROUND
GROUND
GROUND
GROUND
D0 (LSB)
GROUND
COMP
GROUND
AIN
–VREF
+VS
ENCODE
ENCODE
NC = NO CONNECT
GROUND
GROUND
GROUND
GROUND
–VS
+VS
+VREF
+VINT
+VREF
+VS
AIN
–VS
–VREF
+VS
–VS
+VS
+VS
–VS
D7 (MSB)
D0 (LSB)AD9058JD/KD Pinouts
DIGITAL BITS
+VSAD9058 Equivalent Digital Outputs
+5.0V
13kΩ
ENCODEAD9058 Equivalent Encode CircuitAD9058 Burn-In Connections
THEORY OF OPERATIONThe AD9058 contains two separate 8-bit analog-to-digital con-
verters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references and clocks.
In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.
Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating archi-
tecture to reduce circuit complexity, die size and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.
In this unit, each of the two independent ADCs uses only 1287) comparators to make the conversion. The conversion for
the seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.
Analog input range is established by the voltages applied at the
voltage reference inputs (+VREF and –VREF). The AD9058 can
operate from 0 V to +2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quantiza-
tion levels.
ANALOG IN
–VREF
+VREFFigure 1.AD9058 Comparator Block Diagram
The onboard voltage reference, +VINT, is a bandgap reference
which has sufficient drive capability for both reference ladders.
It provides a +2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to +2 V).
USING THE AD9058Refer to Figure 2. Using the internal voltage reference con-
nected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition sys-
tem. The input ranges of the ADCs are positive unipolar in this
configuration, ranging from 0 V to +2 V. Bipolar input signals
are buffered, amplified and offset into the proper input range of
the ADC using a good low distortion amplifier such as the
AD9617 or AD9618.
CLOCK
ENCODE
ANALOG
IN B
±0.5 V
ANALOG
IN A
±0.5 V
0.1µF
20k
0.1µF
0.1µF–
AD9058
ANALOG
IN B
±0.125 V
ANALOG
IN A
±0.125 V
10k10k
0.1µF
+5V
+5V
20k
20k
CLOCK
0.1µF1N4001
RZ1, RZ2 = 2,000Ω SIP (8/PKG)
ENCODE
2N3904
+1V
±1V
–1V
2N3906
±1 V1
0.1µF–Figure 3.AD9058 Using External Voltage References
The AD9058 offers considerable flexibility in selecting the ana-
log input ranges of the ADCs; the two independent ADCs can
even have different input ranges if required. In Figure 3 above,
the AD9058 is shown configured for ±1 V operation.
The Reference Ladder Offset shown in the specifications table re-
fers to the error between the voltage applied to the +VREF (top)
or –VREF (bottom) of the reference ladder and the voltage re-
quired at the analog input to achieve a 1111 1111 or 0000 0000
transition. This indicates the amount of adjustment range which
must be designed into the reference circuit for the AD9058.
The diode shown between ground and –VS is normally reverse
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+VS to be applied before –VS; or the +VS supply is not current
limited. If the negative supply is allowed to float (the +5 V sup-
ply is powered up before the –5 V supply), substantial +5 V
supply current will attempt to flow through the substrate (VS
supply contact) to ground. If this current is not limited to <500
mA, the part may be destroyed. The diode prevents this poten-
tially destructive condition from occurring.
TimingRefer to the AD9058 Timing Diagram. The AD9058 provides
latched data outputs with no pipeline delay. To conserve power,
the data outputs have relatively slow rise and fall times. When
designing system timing, it is important to observe (1) set-up
and hold times; and (2) the intervals when data is changing.
Figure 3 shows 2 kΩ pull-down resistors on each of the D0–D7
logic family devices have short set-up and hold times and are the
recommended choices for speeds of 40 MSPS or more.
LayoutTo insure optimum performance, a single low-impedance ground
plane is recommended. Analog and digital grounds should be
connected together and to the ground plane at the AD9058 de-
vice. Analog and digital power supplies should be bypassed to
ground through 0.1 µF ceramic capacitors as close to the unit as
possible.
An evaluation board (ADI part #AD9058/PCB) is available to
aid designers and provide a suggested layout. The use of sockets
may limit the dynamic performance of the part and is not rec-
ommended except for prototype or evaluation purposes.
For prototyping or evaluation, surface mount sockets are available
from Methode (part #213-0320602) for evaluating AD9058 sur-
face mount packages. To evaluate the AD9058 in through-hole
PCB designs, use the AD9058JD/KD with individual pin sockets
(AMP part #6-330808-0). Alternatively, surface mount AD9058
units can be mounted in a through-hole socket (Circuit Assembly
Corporation, Irvine California part #CA-44SPC-T).
AD9058 APPLICATIONSCombining two ADCs in a single package is an attractive alter-
native in a variety of systems when cost, reliability and space are
important considerations. Different systems emphasize particu-
lar specifications, depending on how the part is used.
In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
