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AD9058AKJ
1.5-2.5V; 20mA; dual 8-bit 50 MSPS A/D converter. For quadrature demodulation for communication, digital oscilloscopes
REV.C
Dual 8-Bit 50 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
QUADRATURE RECEIVER
GENERAL DESCRIPTIONThe AD9058 combines two independent high-performance
8-bit analog-to-digital converters (ADCs) on a single monolithic
IC. Combined with an optional on-board voltage reference,
the AD9058 provides a cost effective alternative for systems
requiring two or more ADCs.
Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high per-
formance and low power (<0.5 watt/channel). Digital inputs
and outputs are TTL compatible.
Performance has been optimized for an analog input of 2 V p-p
(±1 V; 0 V to 2 V). Using the onboard 2 V voltage reference,
the AD9058 can be set up for unipolar positive operation
(0 V to 2 V). This internal voltage reference can drive
both ADCs.
Commercial (0°C to 70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.
FEATURES
Two Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1W)
Low Input Capacitance (10 pF)
65 V Power Supplies
Flexible Input Range
APPLICATIONS
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
Radar
AD9058–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS[�VS = �5 V; VREF = 2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to +2 V; –VREF =
GROUND, unless otherwise noted.]2 All specifications apply to either of the two ADCs.
AD9058DIGITAL OUTPUTS
NOTESAbsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic DIP θJA = 40°C/W; θJC = 12°C/W.To achieve guaranteed conversion rate, connect each data output to ground through a 2 kΩ pull-down resistor.SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
AD9058
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at 25°C, and sample tested at
specified temperatures.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
** INDICATES EACH PIN IS CONNECTED THROUGH 100�
ABSOLUTE MAXIMUM RATINGS1Analog Input . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +2.5 V
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V2
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . 53 mA
+VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V
–VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V
Operating Temperature Range
AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . 0°C to 70°C
Maximum Junction Temperature3
AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C
ORDERING GUIDENOTESD = Hermetic Ceramic DIP Package; J = Leaded Ceramic Package.Hermetically sealed ceramic package; footprint equivalent to PLCC.For specifications, refer to Analog Devices Military Products Databook.
28OUND
OUND
REF
COMPNC
ENCODE
OUND
OUND
OUND
NC
OUND
ENCODE
D7(MSB)
NC = NO CONNECT
GROUND
INT
REF
+VS
–VREF
–VREF
–VS–VS
+VS
D7(MSB)
(LSB)
(LSB)D1AD9058AJJ/AKJ Pinouts
AD9058AJD/AKD Pinouts
PIN FUNCTION DESCRIPTIONS
AD9058
THEORY OF OPERATIONThe AD9058 contains two separate 8-bit analog-to-digital con-
verters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references and clocks.
In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.
Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating archi-
tecture to reduce circuit complexity, die size and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.
In this unit, each of the two independent ADCs uses only 128 (27)
comparators to make the conversion. The conversion for the
seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.
Figure 1.AD9058 Comparator Block Diagram
Analog input range is established by the voltages applied at the
voltage reference inputs (+VREF and –VREF). The AD9058 can
operate from 0 V to +2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quanti-
zation levels.
