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AD9048SE/883B-AD9048SQ/883B-AD9048TQ/883B
Monolithic 8-Bit Video A/D Converter
Monolithic 8-BitVideo A/D Converter
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9048 is an 8-bit, 35 MSPS flash converter, made on
a high speed bipolar process, which is an alternate source for
the TDC1048 unit, and offers enhancements over its
predecessor. Lower power dissipation makes the AD9048
attractive for a variety of system designs.
Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic, and output
buffer registers operating at minimum rates of 35 MSPS pre-
clude a need for a sample-and-hold (S/H) or track-and-hold
(T/H) in most system designs using the AD9048. All digital
control inputs and outputs are TTL compatible.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
0.5 LSB or 0.75 LSB can be ordered for a commercial range of
0°C to 70°C or extended case temperatures of –55°C to +125°C.
Commercial versions are packaged in 28-lead DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
The AD9048 A/D converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9048/883B data sheet for detailed
specifications.
FEATURES
35 MSPS Encode Rate
16 pF Input Capacitance
550 mW Power Dissipation
Industry-Standard Pinouts
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)REV.F
AD9048–SPECIFICATIONS(typical with nominal supplies, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS1VCC to DGND . . . . . . . . . . . . . . . . .–0.5 V DC to +7.0 V DC
AGND to DGND . . . . . . . . . . . . . .–0.5 V DC to +0.5 V DC
VEE to AGND . . . . . . . . . . . . . . . . .+0.5 V DC to –7.0 V DC
VIN, VRT, or VRB to AGND . . . . . . . . . . . . . . . . . 0.5 V to VEE
VRT to VRB . . . . . . . . . . . . . . . . . . . .–2.2 V DC to +2.2 V DC
CONV, NMINV or NLINV to DGND–0.5 V DC to +5.5 V DC
Applied Output Voltage to DGND –0.5 V DC to +5.5 V DC2
Applied Output Current, Externally Forced
. . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 mA to +6.0 mA3, 4
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . 1.0 sec5
Operating Temperature Range (Ambient)
AD9048JJ/KJ/JQ/KQ . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD9048SE/SQ/TE/TQ . . . . . . . . . . . . . .–55°C to +125°C
Maximum Junction Temperature (Plastic) . . . . . . . . .150°C6
Maximum Junction Temperature (Hermetic) . . . . . . .150°C6
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
(VCC = +5.0 V; VEE = –5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted.)
DIGITAL OUTPUTS
NOTES
1Maximum ratings are limiting values to be applied individually, and beyond which
the serviceability of the device may be impaired. Functional operation under any of
these conditions is not necessarily implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect device reliability.
2Applied voltage must be current-limited to specified range.
3Forcing voltage must be limited to specified range.
4Current is specified as negative when flowing into the device.
5Output High; one pin to ground; 1s duration.
6Typical thermal impedances (no air flow) are as follows:
Ceramic DIP: θJA = 49°C/W, θJC = 15°C/W; LCC: θJA = 69°C/W, θJC = 21°C/W;
JLCC: θJA = 59°C/W; θJC = 19°C/W.
To calculate junction temperature (TJ), use power dissipation (PD) and thermal
impedance: TJ = PD (θJA) + TAMBIENT = PD (θJC) = + TCASE.
7Measured with VIN = 0 V and CONVERT low (sampling mode).
8Determined by beat frequency testing for no missing codes.
9VRT ≥ VRB under all circumstances.Outputs terminated with 40 pF and eight 10 Ω pull-up resistors.Interval from 50% point of leading edge CONVERT pulse to change in
output data.For full-scale step input, 8-bit accuracy attained in specified time.Recovers to 8-bit accuracy in specified time after –3 V input overvoltage.Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences.Measured at 20 MHz encode rate with analog input 1 dB below full scale.Measured at 35 MHz encode rate with analog input 1 dB below full scale.RMS signal to rms noise.Peak signal to rms noise.DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading;
20 MHz encode.Clock frequency = 4 × NTSC = 14.32 MHz. Measured with 40-IRE
modulated ramp.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELSTest Level I–100% production tested.
Test Level II–100% production tested at 25°C and
sample tested at specific temperatures.
Test Level III–Sample tested only.
Test Level IV–Parameter is guaranteed by design and
characterization testing.
Test Level V–Parameter is a typical value only.
Test Level VI–All devices are 100% production tested at
25°C. 100% production tested at temperature
extremes for military temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.
AD9048
AD9048
ORDERING GUIDENOTESE = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; D = Cerdip.MIL-STD-883 and Standard Military Drawing available.
PIN CONFIGURATIONS
MECHANICAL INFORMATIONDie Dimensions . . . . .140 mils × 137 mils × 21 mils (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . .4 mils × 4 mils
Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VEE
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic
Bond Wire . . . . . . . . . . . . . . .1 mils Gold; Gold Ball Bonding
DIP (D Package)
LCC (E Package)27131415161718
NC = NO CONNECT
AGND
VIN
AGND
DGND
VCC
VEE
VEE
VEE
VCC
DGNDD2D1 (MSB)
NLINVD6D7
(LSB) D8
CONVERT
NMINV
J-Leaded Ceramic (J Package)
CONVERT
D8 (LSB)
NLINV
NMINV
(MSB) D1
AGNDNCNCAGND
DGND
DGND
NC = NO CONNECT
RLOW
RMID
NMINV
MSB
RTOP
CONV
NLINV
DGND
DGND
AGNDAINAGND
VCCVEEVCCVCCVCCVEEVEE
DGNDFigure 1.Bonding Diagram
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9048 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
PIN FUNCTION DESCRIPTIONSFigure 2.Burn-In Diagram
VEE
CONVERT
AD9048
THEORY OF OPERATIONRefer to the Functional Block Diagram of the AD9048. The
AD9048 comprises three functional sections: a comparator
array, encoding logic, and output latches.
Within the array, the analog input signal to be digitized is
compared with 255 reference voltages. The outputs of all com-
parators whose references are below the input signal level will be
high; outputs whose references are above that level will be low.
The n-of-255 code that results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.
After encoding, the signal is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which com-
parator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.
Input signal levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative out-
puts. No damage will occur to the AD9048 as long as the input
is within the voltage range of VEE to 0.5 V.
The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.
Applications that depend on controlled phase shift at the con-
verter input can benefit from using the AD9048 because of its
inherently lower phase shift.
The CONVERT, analog input, and digital output circuits are
shown in Figure 3.
System timing, which provides details on delays through the
AD9048 as well as the relationships of various timing events, is
shown in Figure 4.
Figure 4.Timing Diagram
Dynamic performance of the AD9048, i.e., typical signal-to-
noise ratio, is illustrated in Figures 5 and 6.
Figure 5.Dynamic Performance (20 MHz Encode Rate)
Figure 6.Dynamic Performance (35 MHz Encode Rate)
