AD9040AJN-AD9040AJR Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9040AJN-AD9040AJR
10-Bit 40 MSPS A/D Converter
REV.B10-Bit 40 MSPS
A/D Converter
FEATURES
Low Power: 940 mW
53 dB SNR @ 10 MHz AIN
On-Chip T/H, Reference
CMOS-Compatible
2 V p-p Analog Input
Fully Characterized Dynamic Performance
APPLICATIONS
Ultrasound Medical Imaging
Digital Oscilloscopes
Professional Video
Digital Communications
Advanced Television (MUSE Decoders)
Instrumentation
GENERAL DESCRIPTION
The AD9040A is a complete 10-bit monolithic sampling analog-
to-digital converter (ADC) with on-board track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only an encode signal to achieve
40 MSPS sample rates with 10-bit resolution.
Digital inputs and outputs are CMOS compatible; the analog
input requires a signal of 2 V p-p amplitude. The two-step
architecture used in the AD9040A is optimized to provide the
best dynamic performance available while maintaining low
power requirements of only 940 mW typically; maximum dissi-
pation is 1.1 watt at 40 MSPS.
The signal-to-noise ratio (SNR), including harmonics, is 53 dB,
or 8.5 ENOB, when sampling an analog input of 10.3 MHz at
40 MSPS. Competitive devices perform at less than 7.5 ENOB
and require external references and larger input signals.
The AD9040A A/D converter is available as either a 28-lead
plastic DIP or a 28-lead SOIC. The two models operate over a
commercial temperature range of 0°C to +70°C. Contact the
factory regarding availability of ceramic military temperature
range devices.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTSCMOS compatible logic for direct interface to ASICs.On-board T/H provides excellent high frequency perfor-
mance on analog inputs, critical for communications and
medical imaging applications.High input impedance and 2 volt p-p input range reduce
need for external amplifiers.Easy to use; no cumbersome external voltage references
required, allowing denser packing of ADCs for multichannel
applications.Available in 28-lead plastic DIP and SOIC packages.Evaluation board includes AD9040AJR, reconstruction
DAC, and latches. Space is available near the analog input
and digital outputs of the converter for additional circuits.
Order as part number AD9040A/PCB (schematic shown in
data sheet).
AD9040A–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
BANDGAP REFERENCE
(+VS = VD = +5 V; –VS = –5 V; internal reference: ENCODE = 40.5 MSPS unless
otherwise noted)
DIGITAL OUTPUTS
POWER SUPPLY
NOTES“Gain Tempco” is for converter using internal reference; “Temperature
Coefficient” is for bandgap reference only.Output propagation delay (tPD) is measured from the 50% point of the falling
edge of the encode command to the min/max voltage levels of the digital
outputs with 10 pF maximum loads.RMS signal to rms noise with analog input signal 1 dB below full scale at
specified frequency.ENCODE = 32 MSPS.3rd order intermodulation measured with analog input frequencies of 2.3 MHz
and 2.4 MHz at 7 dB below full scale.For rated performance at 40 MSPS, duty cycle of encode command should be
50% –10%.Measured as the ratio of the change in offset voltage for a 5% change in +VS
or –VS.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.–100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for military
temperature devices; guaranteed by design and character-
ization testing for industrial devices.
ABSOLUTE MAXIMUM RATINGS1VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS to +VS
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +VS
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature
AD9040AJN/JR . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature2 (JN/JR Suffixes) . . . +150°C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . .+300°C
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances (parts soldered to board):
N Package (Plastic DIP): qJA = 42°C/W; qJC = 10°C/W.
R Package (SOIC): qJA = 47°C/W; qJC = 10°C/W.
ORDERING GUIDE
AD9040A
PIN FUNCTION DESCRIPTIONS
NC = NO CONNECT
GND
AIN
–VS
GND
+VS
ENCODE
–VS
GND
+VS
GND
BPREF
VREF
VOUT
D9 (MSB)
–VS
D0 (LSB)
GND
PDIP and SOIC Pinouts
ENCODE
GND
+VS
VREF
VOUT
D0 (LSB)
GND
D9 (MSB)OR
GND
GNDA
BPREF
DGND
–VS
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . .204 · 185 · 21 (–1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 · 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5,070
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Oxynitride
N + 1#3
ENCODE
tPD
AIN
DIGITAL
OUTPUTS
APERTURE DELAY
PULSEWIDTH HIGH
PULSEWIDTH LOW
OUTPUT PROP DELAY
tEH
tEL
tPD
10ns
MINTYPMAX100
Figure1. Timing Diagram
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the rising edge of the ENCODE command
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Gain
The percentage of amplitude change of a small high frequency
sine wave (3.58 MHz) superimposed on a low frequency signal
(15.734 kHz).
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Differential Phase
The phase change of a small high frequency sine wave (3.58 MHz)
superimposed on a low frequency signal (15.734 kHz).
Harmonic Distortion
The rms value of the fundamental divided by the rms value of
the harmonic.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” de-
termined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency tested drops by no more than 3 dB below the guaran-
teed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the falling edge of the
ENCODE command and the 1 V/4 V points of output data.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
10-bit accuracy after an analog input signal 150% of full scale is
reduced to the full-scale range of the converter.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude to the rms value of
“noise,” which is defined as the sum of all other spectral com-
ponents, including harmonics but excluding dc, with an analog
input signal 1 dB below full scale.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude to the rms value of
“noise,” which is defined as the sum of all other spectral com-
ponents, excluding the first eight harmonics and dc, with an
analog input signal 1 dB below full scale.
Transient Response
The time required for the converter to achieve 10-bit accuracy
when a step function is applied to the analog input.
Two-Tone Intermodulation Distortion (IMD) Rejection
The ratio of the power of either of two input signals to the
power of the strongest third-order IMD signal.
VCC
VSS
AIN1mA
1kV
ANALOG INPUT
VCC
VREF
GND
VSS
REFERENCE CIRCUIT
VCC
VOUT
GND
BANDGAP OUTPUT
VCC
GND
D0-9
CMOS OUTPUT1kV
Figure 2.Equivalent Circuits
AD9040A
THEORY OF OPERATION
Refer to the block diagram.
The AD9040A employs subranging architecture and digital error
correction. This combination of design techniques insures true
10-bit accuracy at the digital outputs of the converter.
At the input, the analog signal is applied to a track-and-hold
(T/H) that holds the analog value which is present when the
unit is strobed with an ENCODE command. The conversion
process begins on the rising edge of this pulse, which should
have a 50% (–10%) duty cycle. Minimum encode rate of the
AD9040A is 10 MSPS because of the use of three internal T/H
devices.
The held analog value of the first track-and-hold is applied to a
5-bit flash converter and a pair of internal T/Hs (shown in the
block diagram as a single unit). The T/Hs pipeline the analog
signal to the amplifier array through a residue ladder and switch-
ing circuit while the 5-bit flash converter resolves the most
significant bits (MSBs) of the held analog voltage.
When the 5-bit flash converter has completed its cycle, its out-
put activates 1-of-32 ladder switches; these, in turn, cause the
correct residue signal to be applied to the error amplifier array.
The output of the error amplifier is applied to a 6-bit flash con-
verter whose output supplies the five least significant bits (LSBs)
of the digital output along with one bit of error correction for
the 5-bit main range converter.
Decode logic aligns the data from the two converters and pre-
sents the result as a 10-bit parallel digital word. The output
stage of the AD9040A is CMOS. Output data are strobed on
the trailing edge of the ENCODE command.
Full-scale range of the AD9040A is determined by the reference
voltage applied to the VRFF (Pin 6) input. This voltage sets the
internal flash and residue ladder voltage drops; these establish
the value of the LSB. Because of headroom restraints, the full-
scale range cannot be increased by applying a higher-than
specified reference voltage. Conversely, a lower reference volt-
age will reduce the full-scale range of the converter, but will also
decrease its performance. An internal bandgap reference voltage
of +2.5 V is provided to assure optimum performance over the
operating temperature range.
USING THE AD9040A
Timing
The duty cycle of the encode clock for the AD9040A is critical
for obtaining rated performance of the ADC. Internal pulse
widths within the track-and-hold are established by the encode
command pulse width; to ensure rated performance, the duty
cycle should be held at 50%. Duty cycle variations of less than10% will cause no degradation in performance.
Operation at encode rates less than 10 MSPS is not recom-
mended. The internal track-and-hold saturates, causing errone-
ous conversions. This T/H saturation precludes clocking the
AD9040A in burst mode. The 50% duty cycle must be main-
tained even for sample rates down to 10 MSPS.
The AD9040A provides latched data outputs, with 2 1/2 pipe-
line delays. Data outputs are available one propagation delay
(tPD) after the falling edge of the encode command (refer to
AD9040A Timing Diagram). The length of the output data
lines and the loads placed on them should be minimized to
reduce transients within the AD9040A; these transients can
detract from the converter’s dynamic performance.
Voltage Reference
A stable voltage reference is required to establish the 2-V p-p
range of the AD9040A. There are two options for creating this
reference. The easiest and least expensive way to implement it is
to use the (+2.5 V) bandgap voltage reference which is internal
to the ADC. Figure 3 illustrates the connections for using the
internal reference. The internal reference has 500 mA of extra
drive current which can be used for other circuits.
Figure 3.Using Internal Reference
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain (input
range) of the AD9040A which cannot be obtained by using the
internal reference. For these applications, an external +2.5 V
reference can be used, as shown in Figure 4. The VREF input
requires 5 mA of drive current.
Figure 4.Using External Reference

Partno	Mfg	Dc	Qty	Available	Descript
AD9040AJN	AD	N/a	4	avai	10-Bit 40 MSPS A/D Converter
AD9040AJR		N/a	3	avai	10-Bit 40 MSPS A/D Converter