AD9012BQ ,High Speed 8-Bit TTL A/D ConverterCHARACTERISTICS (+V = +5.0 V; –V = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwis ..
AD9012SQ/883B ,High Speed 8-Bit TTL A/D ConverterCHARACTERISTICS (+V = +5.0 V; –V = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise ..
AD9020JE ,10-Bit 60 MSPS A/D ConverterGENERAL DESCRIPTION 23 D4L CR 1024 10R22 DThe AD9020 A/D converter is a 10-bit monolithic converter ..
AD9020JZ ,10-Bit 60 MSPS A/D ConverterCHARACTERISTICS (6V = 65 V; 6V = 61.75 V; ENCODE = 40 MSPS unless otherwise noted)S SENSETest AD902 ..
AD9020KE ,10-Bit 60 MSPS A/D ConverterSPECIFICATIONS1ABSOLUTE MAXIMUM RATINGS 3/4 , 1/2 , 1/4 Current . . . . . . . . . . . . . . . . . . ..
AD9020KZ ,10-Bit 60 MSPS A/D Converterspecifications.4Measured with ANALOG IN = +V .SENSE5Output delay measured as worst-case time from 5 ..
ADS5421Y/T ,14 Bit,40MSPS Sampling ADCPIN CONFIGURATIONTop View TQFP64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49+V 1 48 GNDSA+V 2 47 G ..
ADS5422Y/250 ,14-Bit, 62MSPS Sampling ADC
ADS5423IPGP ,A 5V 14bit, 80MSPS Analog-to-Digital Converter 52-HTQFP -40 to 85FEATURESHeatsink 14 Bit Resolution Pin Compatible to the AD6644/45 80 MSPS Maximum Sample Rate ..
ADS5423IPJY ,14 Bit, 80 MSPS Analog-to-Digital ConverterBLOCK DIAGRAMAV DRVDD DDA+ +INA2 TH3 A3TH2A1 TH1 Σ Σ ADC3AIN− −ADC1 DAC1 ADC2 DAC2VREF Reference5 5 ..
ADS5423IPJYRG3 , A 5V 14bit, 80MSPS Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS Over full temperature range (T = −40°C to T = 85°C), sampling rate = 80 ..
ADS5423IPJYRG4 ,14 Bit, 80 MSPS Analog-to-Digital ConverterMAXIMUM RATINGSsusceptible to damage because small parametric changes could cause(1)over operating ..
AD9012AJ-AD9012AQ-AD9012BQ
High Speed 8-Bit TTL A/D Converter
REV. D
High Speed 8-Bit
TTL A/D Converter
GENERAL DESCRIPTIONThe AD9012 is an 8-bit, ultrahigh speed, analog-to-digital
converter. The AD9012 is fabricated in an advanced bipolar
process that allows operation at sampling rates up to one hun-
dred megasamples/second. Functionally, the AD9012 is com-
prised of 256 parallel comparator stages whose outputs are
decoded to drive the TTL compatible output latches.
The exceptionally wide large-signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9012 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold. The
comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9012 is available in two grades: one with 0.5 LSB linear-
ity and one with 0.75 LSB linearity. Both versions are offered in
FEATURES
100 MSPS Encode Rate
Very Low Input Capacitance—16 pF
Low Power—1 W
TTL Compatible Outputs
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Guidance
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
FUNCTIONAL BLOCK DIAGRAMan industrial grade, –25°C to +85°C, packaged in a 28-lead DIP
and a 28-lead JLCC. The military temperature range devices,
–55°C to +125°C, are available in ceramic DIP and LCC pack-
ages and are compliant to MIL-STD-883 Class B.
The AD9012 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Databook
or current AD9012/883B data sheet for detailed specifications.
AD9012–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+VS = +5.0 V; –VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
AD9012
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
NOTES
1Measured with Analog Input = 0 V.Measured by FFT analysis where fundamental is –3 dBc.
3Input slew rate derived from rise time (10% to 90%) of full-scale step input.Outputs terminated with two equivalent ’LS00 type loads. (See load circuit.)
5Measured from ENCODE into data out for LSB only.For full-scale step input, 8-bit accuracy is attained in specified time.
7Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage.
8Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences.ENCODE signal rise/fall times should be less than 30 ns for normal operation.Measured at 75 MSPS encode rate. Harmonic data based on worst case harmonics.Analog input frequency = 1.23 MHz.RMS signal to rms noise, including harmonics with 1.23 MHz. analog input
signal.NPR measured @ 0.5 MHz. Noise Source is 250 mW (rms) from 0.5 MHz
to 8 MHz.Supplies should remain stable within –5% for normal operation.Measured at –5.2 V – 5% and +5.0 V – 5%.
Specifications subject to change without notice.
ORDERING GUIDE*E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier;
Q = Cerdip.
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; guaranteed by design and
characterization testing for industrial devices.
ABSOLUTE MAXIMUM RATINGS1Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . .+6 V
Analog to Digital Supply Voltage Differential (–VS) . . . .0.5 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . .–6 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . .–VS to +0.5 V
ENCODE Input Voltage . . . . . . . . . . . . . . . . .–0.5 V to +5 V
OVERFLOW INH Input Voltage . . . . . . . . . . .–5.2 V to 0 V
Reference Input Voltage (+VREF –VREF)2 . . . .–3.5 V to +0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . .2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . .–4 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .30 mA
Operating Temperature Range
AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . .. . . . –25°C to +85°C
AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . .. . . . –65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
NOTESAbsolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.+VREF ‡ –VREF under all circumstances.Maximum junction temperature (tJ max) should not exceed +175°C for ceramic
packages, and +150°C for plastic packages:
tJ = PD (qJA) + tA
PD (qJC) + tc
where
PD = power dissipation
qJA = thermal impedance from junction to ambient (°C/W)
qJC = thermal impedance from junction to case (°C/W)
tA = ambient temperature (°C)
tC = case temperature (°C)
typical thermal impedances are:
Ceramic DIP qJA = 42°C/W; qJC = 10°C/W
Ceramic LCC qJA = 50°C/W; qJC = 15°C/W
JLCC qJA = 59°C/W; qJC = 15°C/W.
Recommended Operating ConditionsFigure 1.Load Circuit
AD9012
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
DIGITAL VS+
REFMID
–VREF
ANALOG INPUT
ANALOG GROUND
DIGITAL VS+
DIGITAL VS+
OVERFLOW INH
HYSTERESIS
+VREF
ENCODE
ANALOG GROUND
ANALOG INPUT
D1 (LSB)
DIGITAL GROUND
ANALOG VS–
DIGITAL VS–
OVERFLOW
D8 (MSB)
ANALOG VS–
DIGITAL GROUND
DIGITAL VS–27123426131415161718
DIGITAL GROUND
ANALOG VS–
ANALOG VS–
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL VS+
ANALOG INPUT
–VREF
REF
HYSTERESISOVERFLOW INHDIGITAL V
DIGITAL V
OVERFLOWD
(MSB)
REF
MID
DIGITAL V
DIGITAL V
(LSB)
DIGITAL GROUND
ANALOG GROUND
Figure 2.Timing Diagram
1VREF
2VREF
25.2V
256 COMPARATOR
CELLS
REFMID
ANALOG
INPUTENCODE15.0V
DIGITAL
OUTPUTS15.0V
Figure 3.Input Output Circuits
DIE LAYOUT AND MECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . . .111 · 123 · 15 (–2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 · 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
Die Attach . . . . . . . . . . . . . . . . . . . .Gold Eutectic (Ceramic)
ALL RESISTORS 6 5%
ALL CAPACITORS 6 20%
ALL SUPPLY VOLTAGES 6 5%
AD1
AD2
–2.0V
–5.2V+5.0V
ONE JUMPER
PER BOARD
OPTION #1 (STATIC) AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC) SEE WAVEFORMS
–2V
+2.4V
+0.4V
AD1
AD2
LOAD
RESISTORSFigure 4.Burn-In Diagram
AD9012
APPLICATION INFORMATIONThe AD9012 is compatible with all standard TTL logic fami-
lies. However, to operate at the highest encode rates, the sup-
porting logic around the AD9012 will need to be equally fast.
Two possible choices are the AS and the ALS families. Which-
ever of the TTL logic families is used, special care must be
exercised to keep digital switching noise away from the analog
circuits around the AD9012. The two most critical items are the
digital supply lines and the digital ground return.
The input capacitance of the AD9012 is an exceptionally low
16 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the
160 MHz input bandwidth of the AD9012, a hybrid amplifier
like the AD9610/AD9611 will be required. For those applica-
tions that do not require the full input bandwidth of the AD9012,
some of the more traditional monolithic amplifiers, like the
AD846, should work very well. Overall performance with mono-
lithic amplifiers can be improved by inserting a 40 W resistor in
series with the amplifier output.
The output data is buffered through the TTL compatible out-
put latches. In addition to the latch propagation delay (tPD), all
data is delayed by one clock cycle, before becoming available at
the outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising edge
of the TTL-compatible ENCODE signal (see timing diagram).
The AD9012 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INHIBIT pin of the AD9012 determines
how the converter handles overrange inputs (AIN ‡ + VREF). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW for overrange inputs, and all other digital out-
puts will be at logic HIGH (nonreturn-to-zero operation).
The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER-
ESIS control pin). This level of performance is extremely impor-
tant in fault sensitive applications such as digital radio (QAM).
Dramatic improvements in comparator design and construction
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The 160 MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47 dB with
a 1.23 MHz input. High SNR performance is particularly im-
portant in broadcast video applications where signals may pass
through the converter several times before the processing is
complete. Pulse signature analysis, commonly performed in
advanced radar receivers, is another area that is especially
dependent on high quality dynamic performance.
LAYOUT SUGGESTIONSDesigns using the AD9012, like all high-speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high-speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9012. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should
be connected together at the AD9012 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention
involves the three reference inputs, +VREF, REFMID, and –VREF.
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in im-
proving the integral linearity by correcting any reference ladder
skews.
The reference inputs should be adequately decoupled to ground
through 0.1 mF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 mF and
0.01 mF chip capacitors should be very effective.
The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical
connections. Otherwise, aperture delay errors may degrade
converter performance at high frequencies.
0.1mF
AD9611
TTL
ENCODE
INPUT
ANALOG
INPUT
(0 TO +2V)
–15V
50VFigure 5.Typical Application
