AD9002AD ,High Speed 8-Bit Monolithic A/D ConverterGENERAL DESCRIPTIONBIT 2The AD9002 is an 8-bit, high speed, analog-to-digital converter.RThe AD9002 ..
AD9002AJ ,High Speed 8-Bit Monolithic A/D ConverterSpecifications subject to change without notice.–2– REV. DAD90021ABSOLUTE MAXIMUM RATINGS Recommend ..
AD9012AJ ,High Speed 8-Bit TTL A/D ConverterGENERAL DESCRIPTION D2The AD9012 is an 8-bit, ultrahigh speed, analog-to-digitalRD (LSB)converter. ..
AD9012AQ ,High Speed 8-Bit TTL A/D ConverterSpecifications subject to change without notice.1ABSOLUTE MAXIMUM RATINGSVSPositive Supply Voltage ..
AD9012BQ ,High Speed 8-Bit TTL A/D ConverterCHARACTERISTICS (+V = +5.0 V; –V = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwis ..
AD9012SQ/883B ,High Speed 8-Bit TTL A/D ConverterCHARACTERISTICS (+V = +5.0 V; –V = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise ..
ADS5400IPZP ,12-bit, 1000 MSPS ADC with analog input buffer 100-HTQFP -40 to 85Features 3 DescriptionThe ADS5400 device is a 12-bit, 1-GSPS analog-to-1• 1-GSPS Sample Ratedigital ..
ADS5400IPZPR ,12-bit, 1000 MSPS ADC with analog input buffer 100-HTQFP -40 to 85FEATURES list. 1• Deleted text "Internal pull-down resistor" from the SCLK, SDIO, and SDO pins in t ..
ADS5410IPFB ,12-Bit, 80 MSPS ADC, Single Ch., Lowest Power, High BW, Excellent PerformanceFEATURES APPLICATIONS 80-MSPS Maximum Sample Rate Cellular Base Transceiver Station ReceiveChann ..
ADS5411IPGP ,11bit 105MSPS Analog-to-Digital Converter 52-HTQFP -40 to 85ELECTRICAL CHARACTERISTICS Over full temperature range (T = −40°C to T = 85°C), sampling rate = 105 ..
ADS5411IPJY , 11bit 105MSPS Analog-to-Digital ConverterMAXIMUM RATINGSsusceptible to damage because small parametric changes could cause(1)over operating ..
ADS5411IPJYR , 11bit 105MSPS Analog-to-Digital ConverterFEATURESHeatsink 11 Bit Resolution Industrial Temperature Range = −40C to 85C 105 MSPS Maximum ..
AD9002AD-AD9002AJ
High Speed 8-Bit Monolithic A/D Converter
REV.D
High Speed 8-Bit
Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
150 MSPS Encode Rate
Low Input Capacitance: 17 pF
Low Power: 750 mW
–5.2 V Single Supply
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Systems
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
GENERAL DESCRIPTIONThe AD9002 is an 8-bit, high speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process that
allows operation at sampling rates in excess of 150 megasamples/
second. Functionally, the AD9002 is comprised of 256 parallel
comparator stages whose outputs are decoded to drive the ECL
compatible output latches.
An exceptionally wide large signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs, without an external track-and-hold.
The comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9002 provides an external hysteresis control pin that
can be used to optimize comparator sensitivity to further im-
prove performance. Additionally, the AD9002’s low power
dissipation of 750 mW makes it usable over the full extended
temperature range. The AD9002 also incorporates an overflow
bit to indicate overrange inputs. This overflow output can be
disabled with the overflow inhibit pin.
The AD9002 is available in two grades, one with 0.5 LSB lin-
earity and one with 0.75 LSB linearity. Both versions are offered
in an industrial grade, –25°C to +85°C, packaged in a 28-lead
DIP and a 28-leaded JLCC. The military temperature range
devices, –55°C to +125°C, are available in ceramic DIP and
LCC packages and comply with MIL-STD-883 Class B.
ELECTRICAL CHARACTERISTICS (–VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)INITIAL OFFSET ERROR
ANALOG INPUT
AC LINEARITY
POWER SUPPLY
AD9002–SPECIFICATIONSNOTESMeasured with AIN = 0 V.
2Measured by FFT analysis where fundamental is –3 dBc.
bit-to-bit time skew differences.ENCODE signal rise/fall times should be less than 10 ns for normal operation.
10Measured at 125 MSPS encode rate.
ABSOLUTE MAXIMUM RATINGS1Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Analog-to-Digital Supply Voltage Differential . . . . . . . . .0.5 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . .–VS to +0.5 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .–VS to 0 V
Reference Input Voltage (+VREF – VREF)2 . . . .–3.5 V to 0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . .2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . .–4 mA
ENCODE to ENCODE Differential Voltage . . . . . . . . . . .4 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature Range
AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . .–25°C to +85°C
AD9002SE/SD/TD/TE . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
NOTESAbsolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect device
reliability.+VREF ‡ –VREF under all circumstances.Maximum junction temperature (tJ max) should not exceed +175°C for ceramic
packages, and +150°C for plastic packages:
tJ = PD (qJA) + tA PD (qJC) + tC
where
PD = power dissipationJA = thermal impedance from junction to ambient (°C/W)qJC = thermal impedance from junction to case (°C/W)
tA = ambient temperature (°C)
tC = case temperature (°C)
Typical thermal impedances are:
Ceramic DIP qJA = 56°C/W; qJC = 20°C/W
Ceramic LCC qJA = 69°C/W; qJC = 23°C/W
PLCC qJA = 60°C/W; qJC = 19°C/W.
Recommended Operating Conditions
EXPLANATION OF TEST LEVELSTest Level I–100% production tested.
Test Level II–100% production tested at +25°C, and
sample tested at specified temperatures.
Test Level III–Sample tested only.
Test Level IV–Parameter is guaranteed by design and
characterization testing.
Test Level V–Parameter is a typical value only.
Test Level VI–All devices are 100% production tested at
+25°C. 100% production tested at tempera-
ture extremes for extended temperature
devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
ORDERING GUIDE*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip
Carrier, J-Formed Leads.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD9002
FUNCTIONAL DESCRIPTION21, 22
24, 25
DIP
LCC27123426
DIGITAL
GROUND
ANALOG –VS
ANALOG –VS
ANALOG INPUT
ANALOGGROUND
ENCODE
ENCODE
ANALOG INPUT
–VREF
REF
HYSTERESISOVERFLOW INHDIGITAL GROUNDDIGITAL –V
OVERFLOW
D8(MSB)
DIGITAL
GROUND
ANALOGGROUND
JLCC
D1(LSB)
DIGITAL –VS
REFMID
D8(MSB)
OVERFLOW
DIGITAL –VS
DIGITALGROUND
OVERFLOW INH
HYSTERESIS
+VREFD6DIGITAL GROUNDANALOG –V
DIGITAL GROUNDD5
ANALOG –V
DIGITAL
GROUND
PIN DESIGNATIONS
Die Dimensions . . . . . . . . . . . . . . . . .106 · 114 · 15 (–2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 · 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Figure 1.Timing Diagram
Figure 2.Input/Output Circuits
AD1
AD2
AD3
1kV
1kV
100V
0.1mF
–5.2V
–2V
STATIC BURN IN
DYNAMIC BURN IN
AD1 = 0V AD2 = ECL HIGH AD3 = ECL LOW
AD1
AD2
AD3
–2V
ECL HIGH
ECL LOW
ECL HIGH
ECL LOW
ALL RESISTORS 6 5%, V
ALL CAPACITORS 6 20%, mF
ALL SUPPLIES 6 5%Figure 3.Burn-in Diagram
Figure 4.Die Layout and Mechanical Information
AD9002
LAYOUT SUGGESTIONSDesigns using the AD9002, like all high speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9002. Separate ground plane areas for the digital and analog
components may be useful, but these separate grounds should
be connected together at the AD9002 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention in-
volves the three reference inputs, +VREF, REFMID, and –VREF.
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in im-
proving the integral linearity by correcting any reference ladder
skews. The application circuit shown below demonstrates a
simple and effective means of driving the reference circuit.
The reference inputs should be adequately decoupled to ground
through 0.1 mF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 mF and
0.01 mF chip capacitors are recommended.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical con-
nections. Otherwise, aperture delay errors may degrade con-
verter performance at high frequencies.
APPLICATION INFORMATIONThe AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL’s logic levels are tempera-
ture compensated, and are therefore compatible with the
AD9002 (and most other ECL device families) only over a
limited temperature range. To operate at the highest encode
rates, the supporting logic around the AD9002 will need to be
equally fast. Whichever of the ECL logic families is used, special
care must be exercised to keep digital switching noise away from
the analog circuits around the AD9002. The two most critical
items are digital supply lines and digital ground return.
The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more tradi-
tional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10 W resistor in series with the amplifier output.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compactible ENCODE signal (see
timing diagram). In applications where only a single-ended
signal is available, the AD96685, a high speed, ECL voltage
comparator, can be employed to generate the differential sig-
nals. All ECL signals (including the overflow bit) should be
terminated properly to avoid ringing and reflection.
The AD9002 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INHIBIT pin of the AD9002 determines
how the converter handles overrange inputs (AIN ‡ +VREF). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW, and all other outputs will be at logic HIGH
for overrange inputs (nonreturn-to-zero operation).
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER-
ESIS control pin). This level of performance is extremely im-
portant in fault-sensitive applications such as digital radio
(QAM).
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is par-
Figure 5.Typical Application
