AD891JP ,RIGID DISK DATA CHANNEL QUALIFIERSPECIFICATIONS
Propagation Delay
20 mV Overdrive
200 mV Overdrive ns
Comparator Mismatch 30 ..
AD891JQ ,RIGID DISK DATA CHANNEL QUALIFIERSPECIFICATIONS
Propagation Delay3 Differentiator Input
to Data Output 6.8 ns
Additional Puls ..
AD9000JD ,High Speed 6-Bit A/D ConverterCHARACTERISTICS unless otherwise noted)Commercial Military08C to +708C –558C to +1258CAD9000JD AD90 ..
AD9002AD ,High Speed 8-Bit Monolithic A/D ConverterGENERAL DESCRIPTIONBIT 2The AD9002 is an 8-bit, high speed, analog-to-digital converter.RThe AD9002 ..
AD9002AJ ,High Speed 8-Bit Monolithic A/D ConverterSpecifications subject to change without notice.–2– REV. DAD90021ABSOLUTE MAXIMUM RATINGS Recommend ..
AD9012AJ ,High Speed 8-Bit TTL A/D ConverterGENERAL DESCRIPTION D2The AD9012 is an 8-bit, ultrahigh speed, analog-to-digitalRD (LSB)converter. ..
ADS5232IPAG ,Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter 64-TQFP -40 to 85SBAS294A–JUNE 2004–REVISED MARCH 2006This integrated circuit can be damaged by ESD. Texas Instrumen ..
ADS5232IPAGG4 ,Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter 64-TQFP -40 to 85FEATURES DESCRIPTION• Single +3.3V SupplyThe ADS5232 is a dual, high-speed, high dynamic• High SNR: ..
ADS5237IPAG ,Dual, 10-Bit, 65MSPS, +3.3V Analog-to-Digital Converter 64-TQFP -40 to 85SBAS420A–AUGUST 2007–REVISED OCTOBER 2007This integrated circuit can be damaged by ESD. Texas Instr ..
ADS5240IPAP ,4-Channel, 12-bit, 40MSPS ADC with Serial LVDS InterfaceFEATURESincoming ADC sampling clock by a factor of 12. This23• Maximum Sample Rate: 40MSPShigh-freq ..
ADS5270IPFP ,8-Channel/ 12-Bit/ 40MSPS ADC with Serial LVDS InterfaceFEATURESincoming ADC sampling clock by a factor of 12. This23• Maximum Sample Rate: 40MSPShigh-freq ..
ADS5271IPFP ,8-Channel, 12-Bit, 40/50MSPS ADC with Serialized LVDS InterfaceThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
AD891JP-AD891JQ
RIGID DISK DATA CHANNEL QUALIFIER
ANALOG
DEVICES
Rigid Disk Data
Channel Qualifier
FEATURES
Three Matched, Offset-Trimmed Comparators
3.1 ns (typl Comparator Propagation Delay
ECL Logic Permits 50 Mbls Transfer Rates
6.8 ns Delay (typ) from Inputs to Data Output
500 ps (typ) Additional Pulse Pairing
Temperature-compensated Operation
Compatible with 10 KH ECL Logic
Two Temperature-compensated One-Shots
One-Shot Periods Set Using External Resistors
PRODUCT DESCRIPTION
The AD891 disk channel qualifier is intended as a companion
chip to the AD890 wideband channel processor. Together, they
comprise a sophisticated package, capable of recovering binary
information from differentiating channels with transfer rates in
excess of 50 megabits per second.
The AD891 provides both level and time-domain qualification.
Level qualification is performed on alternating half cycles of the
data waveform using a user-defined threshold level which is ap-
plied to each of two 3.1 ns propagation delay comparators. This
technique prevents single bit errors from being propagated into
two bit errors. A third comparator is used to provide zero-
crossing detection. Factory trimmed offsets and a careful inter-
nal layout ensure symmetric operation and low pulse pairing
with a differential input waveform.
An external RLC passive delay-line differentiator should be used
with the AD891; the design for a typical network is specified in
detail in the applications section of this data sheet. The use of
an external network permits equal delay times through both the
differentiated and undifferentiated signal paths, thus ensuring
correct centering of the qualification windows, Using the recom-
mended external network also helps ensure optimal signal pass-
band flatness and dispersion.
The outputs from the amplitude-qualification comparators are
applied to the "D" inputs of two master-slave D-type flip-flops
AD891 FUNCTIONAL BLOCK DIAGRAM
Cerdip (Q) Package
F%SITIVE HALF
c MPARATOR
DIFF " 1 + - E] L.EBYEL
(r., - '
DIFF " 2 ZERO 13|AMP+
CROSSING A0891
COMPARATOR
LEVEL 3 015nm.
IN - D ld awn
AMP - 4 a O El Vcc
v RESET FILTER
EE 5 NEGATIVE HALF l " TIME SET
COMPARATOR L -
DIGITAL 6 TIME E) OUTPUT
GND DOMAIN PULSE SET
ONE-SHOT
OUTPUT
DATA -l 7 t9NE-SHOT E] DATA -
which are then clocked by the outputs from the zero-crossing
comparator. Each valid zero-crossing event causes a one-shot
with a user-definable period to be triggered. This disables the
operation of the flip-flops, thus preventing the detection of addi-
tional zero-crossing events during the one-shot period.
Simultaneously, an output one-shot is activated, the leading
edge of which is synchronous with the change in the flip-flop
outputs. The period of this one-shot is also user-definable and is
intended to ensure adequate output pulse duration for transmis-
sion within the external environment. Each one-shot requires a
single metal-film resistor to set its period. All one-shots have
trimmed pulse periods; temperature stability is maintained by
the use of an internal bandgap reference.
The AD891's internal logic consists of temperature-compensated
reduced-swing ECL which exhibits typical propagation delays of
600 ps per gate. The output data conforms to standard 10 KH
ECL logic levels. The AD891 can drive a properly terminated
75 n transmission line.
The AD891 is specified to operate over the commercial (0 to
+70°C) temperature range. It is available either in a 14-pin cer-
dip package or in a 20-pin PLCC package.
MASS STORAGE COMPONENTS 9-15
SPECIFICATIONS (@ +25T and 5 ll de, unless otherwise noted)
Model AD89U
Conditions Min Typ Max Units
COMPARATOR SPECIFICATIONS
Propagation Delay 20 mV Overdrive 3.3 ns
200 mV Overdrive 3.1 ns
Comparator Mismatch 300 ps
Input Offset Voltage 0.25 1.0 mV
Noise Induced Offset Voltage 108 Error Rate 1300 WV
Input Offset Current 100 nA
Input Bias Current 1.6 3 wA
Open-Loop Gain f = 10 MHz 66 dB
Input Resistance Differential 500 k!)
Input Capacitance Differential 1 5 pF
Input Common-Mode Range Referred to Digital GND - 1.5 +2.2 V
INTERNAL LOGIC SPECIFICATIONS
Logic "I'' Level -0,98 -0.85 -0.81 V
Logic "o'' Level - L95 -1.85 - 1.63 V
Rise Time L ns
Fall Time 1.0 ns
D-Type Flip-Flops
Clock - Q Delay 1.3 ns
Clock - Q Delay 1.2 ns
Reset - Q Delay 0.6 ns
Reset - Q Delay 0.55 ns
ONE-SHOT SPECIFICATIONS
Resistor Scalingl One-Shot Pulse w 7+3.l Rser
Pulse Duration RSET = Rmin to R,,,,, 9 180 ns
RSET = 30 kn 95 100 105 ns
ng-r = 10 kn 35 38 41 ns
Resistor Range Rsrrr = Rmin to Rm 0.75 56 kn
EXTERNAL LOGIC SPECIFICATIONS2 T, = +25°C
Output Logic "I'' -0.98 -0.85 -0.81 V
Output Logic "o'' ._.._ 1.95 - 1.85 - 1.63 V
Rise Time 1.4 ns
Fall Time 1.2 ns
DATA THROUGHPUT SPECIFICATIONS
Propagation Delay3 Differentiator Input
to Data Output 6.8 ns
Additional Pulse Pairing' 200 mV Overdrive
5 ns input Rise Time 0 500 1000 ps
Max Transfer Rate 50 Mb/s
Min Transfer Rates 1 Mb/s
POWER SUPPLY REQUIREMENTS
Operating Range
Vcc 4.5 5.0 5.5 V
VEE -4.68 -5.2 -5.72 V
Quiescent Current Tmin to Tmax
Vcc 15 23 35 mA
VEE 55 68 85 mA
lOne-shot pulse in ns; RSET specified in kn.
zLogic specifications obtained for the "Data +" and "Data -" outputs using 1 kn pull-down resistors tied to Va: and 100 ft resistors connected to -2 V.
'Propagation delay is measured from the zero-crossing comparator input to the "Data +" output with 200 mV overdrive.
'Measurements were performed using a t 100 mV square wave having a rise time under 5 ns; this was applied to the input of the zero-crossing comparator. The
resultant pulse pairing is the difference in delay times for two consecutive output pulses.
'The minimum transfer rate is limited only by the maximum recommended one-shot period of 180 ns,
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
9-16 MASS STORAGE COMPONENTS
ABSOLUTE MAXIMUM RATINGS1
SupplyVoltage s.....,.........,.........),
Comparator Differential Input Voltage . . . . . . . . . . . t5.6 V
Storage Temperature Range P, Q ........ -tW'C to + 150°C
Operating Temperature Range2
AD891P, AD891Q ................... 0 to +70°C
Lead Temperature Range (Soldering 60 L/ ....... +300°C
'Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
220-pin PLCC package: 6IA = '70''C/Watt;
14-pin cerdip package: (hA--+105''C/Watt,
PIN CONFIGURATIONS
l4-Pin Cerdip (Q) Package
20-Pin PLCC (P) Package
DIFF- DiFF+ NC IN+ AMP+
Isl Fl Fn Fl Fl
F%SITIVE HALF
DIFF C ' ARATOR E LIENVEL
- - - 2ERO CROSSING - o
COMPARATOR
l L&VEL q nlnc
DIFF - 2 ZERO A0891 " AMP+
CROSSING POSITIVE HALF
COMPARATOR COMPARATOR
LEVEL "gl," - DIGITAL
lN-E L D 316” AMP Ci I CKD " GND
CK L. ex
CK a o
"ap-Ci) tl tl E] Vcc NC 6 D " v
D RESET ct:
RESET RESET RESET
" E NEGATIVE HALF Ciiil FILTER NEGATIVE HALF
COMPARATOR t TIME SET Vee E C0MPARATOR l El NC
I TIME
DIGITALE TIME » 9 OUTPUT DOMAIN
GND DOMAIN PULSE SET ONE-SHOT I FILTER
ONE-SHOT NCI s OUTPUT E TIME SET
OUTPUT A0891 ONE-SHOT
DATA + l: ONE-SHOT El DATA _ I
Ltd be] lnl le) lel
DIGITAL DATA: DATA- NC OUTPUT
GND PULSE SET
ORDERING GUIDE'
Model No. Description Package Option
AD89IJQ 14-Pin Cerdip Q-14
AD89IJP 20-Pin PLCC P-20A
'See Section 20 for package outline information.
MASS STORAGE COMPONENTS 9-17
Typical Characteristics i@ +25°c Mth t5 ll Supplies)
NEGATIVE SUPPLY
< - e....-.---) 1 L7
E w-...----- ,
I " -...- E
5 . /* u "
u: 55 il "
E " a u
A . 's
IO " g
" rosnwE SUPPLY , 2
k---)"'"'" _
- r...-------" 1.1
-Stt 4° -20 tt " 4tt " " '00 "it "0 -6tt -60 ~29 o " to " no 100 no 140
TEMPERATURE - 'C
TEMPERATURE - 'C
Figure 1. Supply Current vs. Figure 2. Comparator Input Bias
Temperature Current vs. Temperature
1.45 "
rosmvs
1.35 "
3 1.25 n
I 2.15 tr
EMS a '
i', 1.95 ii"
8 us E J.
g t.rs 36.3
g t.65 NEGATIVE 'LES
1.55 ti.4
“m -60 -to a 20 40 so an we 120 m -6tt -¢o -20 a 20 w so so 100 120 $40
TEMPERATURE - t TEMPERATURE - "C
Figure 5. Propagation Delay vs.
Temperature
Figure 4, Comparator Common-
Mode Voltage vs. Temperature
R557 = 30k!)
ONE-SHOT PERIOD - us
PROPAGATION DELAY — us
-SD -40 .-2tt . " " "
TEMPERATURE - T
OVERDRWE - mV
Figure 8. One-Shot Period vs.
Temperature
Figure 7. Propagation Delay vs.
Overdrive
9-18 MASS STORAGE COMPONENTS
M 100 120 M0
COMMON-MODE VOLTAGE — Volt:
PROPAGATION DELAY — rIs
ONE-SNOT PERIOD - n:
PollTIVE/
NEGATIVE
v,,,,,,-"'
w,....--'"
" " 6.0
SUPPLY VOLTAGE - thlttlts
4.5 " "
Figure 3. Comparator Common-
Mode Voltage vs. Supply Voltage
cs 5.0
SUPPLY VOLTAGE - Valts
" " 1.0
Figure 6. Propagation Delay vs.
Power Supply Voltage
R5" - Mt
Figure 9. One-Shat Period vs. RSET
Applying the A0891
THEORY OF OPERATION
The AD891 consists of three comparators, two D-type flip-flops,
an internal bandgap reference and a pair of externally adjustable
one-shots. Two comparators are used to provide data amplitude
qualification, and the third acts as a zero-crossing detector when
used with an external passive differentiator circuit. (Refer to the
AD891 block diagram and Figure 11.)
Figure 10 illustrates the operation of the AD891, using the rec-
ommended passive delay-line differentiator described in the fol-
lowing section. Sequence "A" represents the pattern written on
the disk where a logic "I" is a change in magnetic state. Each
change in magnetic state results in an output pulse. The analog
input to the AD891 consists of a sequence of alternating pulses
"B." The data pattern shown is worst case for a 1-7 code input.
"C" represents the output waveform from the external differen-
tiator, such that the points at which zero-crossings occur core-
spond to the peaks of the analog input "B." Sequence "D"
shows the output from the zero-crossing comparator. Changes in
state of this output are used to clock the two internal D-type
WRITE DATA
ANALOG INPUT
TO A0891
0 l 0 1 0 0
POSITIVE - -
THRESHOLD -
NEGATIVE -
THRESHOLD
BIT CELL
DIFFERENTIATOR
OUTPUT I
(INPUT TO ZERO-CROSSING
COMPARATOR) I
ZERO CROSSING
COMPARATOR OUTPUT 0 g
_ -i--
/////7//'/
flip-flops. The flip-flops are enabled using the output "E" from
the positive and negative threshold comparators, such that the
flip-flop outputs change state only when the analog input ex-
ceeds the programmed threshold levels (positive or negative).
When the threshold levels are exceeded and a zero-crossing
event occurs, the flip-flops change state, producing an output
pulse "F ." The duration of this pulse, seen at the Data+/Data--
outputs, is set using an external resistor, as is the internal time-
out which is used to prevent noise induced retriggering. The
final output data sequence is shown in "G." As can be seen,
despite inflections in the analog input, the data is correctly de-
tected and the output is a time-shifted version of the write data.
Since the 1-7 code input is the most demanding of the popular
encoding schemes to qualify, the AD891 is clearly suitable for
other codes, such as MFM and 2-7. The recommended time
domain filter one-shot period for MFM and 1-7 code is equal to
75% of the bit cell clock period. For 2-7 code the one-shot pe-
riod can be increased to 150% of the bit cell clock period.
HO/F‘knl WM B"
i-i-iH-V-l- i-HC-f-
"hc...we2s-'"''h, 1' "C"
LI "D"
THRESHOLD COMPARISON
OUTPUTS OJ - -
__U__-“E
AD891 OUTPUT I
(DATA +IDATA --) o
OUTPUTDATA 0 1 0 1 0 0
UNKNOWN
000010100101"G"
Figure 10. A0891 Operation for Worst Case 1-7 Code Pattern
MASS STORAGE COMPONENTS 9-1.9
