AD890JQ ,V(cc): +-7.5V; precision, wideband channel processing element. For high performance disk subsystem useSpecifications in boldface are tested on all production units at fiaal electrical test. Results fro ..
AD890JQ ,V(cc): +-7.5V; precision, wideband channel processing element. For high performance disk subsystem useFEATURES
An 80 MHz Bandwidth Permitting a so Mbls Data
Transfer Rate
A Variable Gain Amplifi ..
AD891JP ,RIGID DISK DATA CHANNEL QUALIFIERSPECIFICATIONS
Propagation Delay
20 mV Overdrive
200 mV Overdrive ns
Comparator Mismatch 30 ..
AD891JQ ,RIGID DISK DATA CHANNEL QUALIFIERSPECIFICATIONS
Propagation Delay3 Differentiator Input
to Data Output 6.8 ns
Additional Puls ..
AD9000JD ,High Speed 6-Bit A/D ConverterCHARACTERISTICS unless otherwise noted)Commercial Military08C to +708C –558C to +1258CAD9000JD AD90 ..
AD9002AD ,High Speed 8-Bit Monolithic A/D ConverterGENERAL DESCRIPTIONBIT 2The AD9002 is an 8-bit, high speed, analog-to-digital converter.RThe AD9002 ..
ADS5204IPFBRG4Q1 ,Automotive Catalog Dual 10-Bit 40MSPS Low-Power ADC With PGA 48-TQFP -40 to 85FEATURES DESCRIPTIONThe ADS5204 is a dual 10-bit, 40 MSPS analog-to-digital Qualified for Automoti ..
ADS5220 ,12-bit, 40MSPS, +3.3V Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS: AV = +3.3VDDT = –40°C, T = +85°C. Typical values are at T = +25°C, samp ..
ADS5221PFBT , 12-Bit, 65MSPS Sampling, 3.3V ANALOG-TO-DIGITAL CONVERTER
ADS5231IPAG ,Dual low power, 12-bit, 40MSPS ADC 64-TQFP FEATURES DESCRIPTION• Single +3.3V SupplyThe ADS5231 is a dual, high-speed, high dynamic• High SNR: ..
ADS5232IPAG ,Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter 64-TQFP -40 to 85SBAS294A–JUNE 2004–REVISED MARCH 2006This integrated circuit can be damaged by ESD. Texas Instrumen ..
ADS5232IPAGG4 ,Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter 64-TQFP -40 to 85FEATURES DESCRIPTION• Single +3.3V SupplyThe ADS5232 is a dual, high-speed, high dynamic• High SNR: ..
AD890JP-AD890JQ
V(cc): +-7.5V; precision, wideband channel processing element. For high performance disk subsystem use
ANALOG
DEVICES
Precision, Widehand
Channel Processing Element
FEATURES
An 80 MHz Bandwidth Permitting a 50 Mbls Data
Transfer Rate
A Variable Gain Amplifier with 30 dB max Gain
and 40 dB Control Range
Two Gain of 4 RF Buffers
200 n Differential Load Drive Capability
A Pair of Precision Rectifiets
AGC Level and Threshold Outputs
An Averaging, High Gain Sample-and-Hold for
Accurate AGC Operation
Typical Gain Drift in Hold Mode: 0.2 dB/ms
Gains Trimmed and Temperature Compensated
AGC Operation Independent of AGC Level
Symmetrical AGC AttackIDecay Times
q us AGC Attack/Decay Times Using a 1000 pF
External Capacitor
Suitable for Use as an Accurate Video Programmable
Gain Amplifier
Dynamic Clamp Ensures Fast Recovery After Write to
Read Transients
AGC RF Output Level ts Internally Preset
PRODUCT DESCRIPTION
The AD890 is primarily intended for high performance disk
subsystem use, and as such it is configured around the classic
read channel processing block diagram. It is intended to be con-
nected between the head preamplifier and the qualification cir-
cuitry required for digital data recovery. When used with the
AD891 rigid disk data qualif1er, data transfer rates in excess of
50 Mbls can be processed.
A temperature-compensated AGC loop, with an exponential
transfer characteristic, permits optimal settling and allows for
predictable performance in the classic single integrator control
loop configuration. Fast acquisition and low droop while in the
hold mode allow for AGC operation to be performed within the
sector header without compromising channel behavior when
reading data.
The AD890 processing element has the flexibility to perform
both continuous and sampled AGC functions; it is also ideal for
embedded, dedicated, or mixed servo applications. Two user-
defmed filter/equalizer stages may be employed, thus allowing
maximum design flexibility. This greatly simplifies the design
of the overall channel characteristics. Using the AD890, the de-
signer no longer needs to resort to passive techniques to isolate
network functions; this avoids problems of signal loss and inter-
action. Two low offset, 100 MHz, full wave rectifiers provide
the capability to track a l V peak signal. The rectifrer generating
AD890 FUNCTIONAL BLOCK DIAGRAM
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the "Qualifier Threshold" output may be used for creating a
data qualification level. A second rectifier is used to drive the
sample-and-hold circuitry.
The 80 MHz bandwidth of the AD890 ensures good phase lin-
earity up to 50 MHz. Thus, data transfer rates in excess of
50 Mbls can be supported with good error rates and predictable
channel behavior.
The AD890 is available in both a 24-pin, slim-line cerdip pack-
age and in a 28-pin PLCC package and is specified to operate
over the 0 to +70°C commercial temperature range.
MASS STORAGE COMPONENTS P-
SPECIFICATIONS (@ +25°C and tii y de, unless othemise noted)
AD890]
Parameter . Conditions Min Typ Max Units
VARIABLE GAIN AMPLIFIER
Maximum Gainl 29.0 30.0 31.0 dB
t3 dB Bandwidth Up to 40 dB Gain Reduction 100 MHz
Input Resistance Differential 12 18 kft
Input Capacitance Differential 1 5 pF
Input Voltage Noise 0 dB Gain Reduction 5 nv/vFie
Input Signal Range Recommended ir-p Differential 10 200 mV
Max Output Signal Level 1 k0 Load, p-p Differential L4 V
Output Impedance 5 n
Output DC Level 3.5 V
Harmonic Distortion 0 dB Gain Reduction 0.15 %
26 dB Gain Reduction 1.5 %
INPUT CLAMPZ
Turn-On Time 30 ns
Tum-Off Time 200 ns
Input Signal Attenuation 35 dB
On-State Input Impedance Differential 14 n
GAIN OF 4 BUFFER
Nominal Gain 12.25 12.75 13.25 dB
Gain Variation Tmin to Tmax t0.25 dB
t3 dB Bandwidth Up to 26 dB Gain Reduction 160 MHz
Input Resistance Differential 100 kft
Input Capacitance Differential 1 S pF
input Voltage Noises 100 MHz - 0 dB Gain Reduction 7 nV/V'Hz
Input Common-Mode Range - 1.5 +1.5 V
Output Impedance 10 n
Output Signal Level Recommended p-p Differential 1.3 V
Max Output Signal Level 200 ft Load, p-p Differential 4.8 V
Output DC Level 2.5 V
Harmonic Distortion 300 mV Peak Output, 200 ft Load 0.20 %
FULL WAVE RECTIFIER
Input Signal Level p-p Differential 0.3 3 V
-3 dB Bandwidth 100 mV @1 V Peak Input 100 MHz
Max Output Signal Level 1.5 V
Output Impedance' 25
DC Offset' Relative to Ground 10 t20 mV
AGC CONTROL SECTION
Attack Time 26 dB Gain Step - 1000 pF CSAMPLE 1.0 as
26 dB Gain Step - <50 pF CSAMPLE 120 ns
Hold Time 1 dB Gain Change - 1000 pF Csmpu: 10 ms
AGC Charge Current 0.8 mA
AGC Control Range 36 40 dB
AGC Control Sensitivity Per 20 mV Input 1 dB
AGC Control Linearity 26 dB AGC Range 10.25 dB
Set Level Input Range For Specified Accuracy 0 800 mV
Nondestructive Input Range -0.3 Vcc V
MODE CONTROL SECTION
TTL Compatible
Vu, 2.0 V
IL 0.8 V
Im Vm = 2.7 Volts 1 "
IL " = 0.4 Volts -4.5 -12.0 "
Mode Switching Times 50 ns
POWER SUPPLY REQUIREMENTS
Operating Range Vcc +4.5 +5.5 V
Operating Range VEE -4.68 -5.2 -5.72 V
Quiescent Current Tmin to Tm
Vcc Hold/Acquire/Set Gain Mode 44 60 76 mA
VEE Hold/Acquire/Set Gain Mode 18 28 40 mA
cc Clamp Mode 51 72 88 mA
VEE Clamp Mode 17 27 39 mA
9-8 MASS STORAGE COMPONENTS
'Gain calibrated in gain set mode with 0 volts applied to the Gain Set Pin.
‘Clamp operation is specified with a source impedance of 200 n in series with 0.1 M'.
'Over the full 100 MHz bandwidth of the AD890, the worst-case rms signal-to-noise ratio is 40 dB or better with a 40 dB AGC range.
'Measured using a 4 kn resistor connected between the Qualifier Threshold Pin and Visa-
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are
used to calculate outgoing quality levels.
Specifications subiect to change without notice.
ABSOLUTE MAXIMUM RATINGS'
SupplyVoltage o........................."
RF Gain Stage Differential Input Voltage . . . . . . . . . 15.6 V
Storage Temperature Range
AD89OJP, AD89OJQ .............. -65''C to +150°C
Operating Temperature Range'
AD89OJP, AD89OJQ ................... 0 to +70°C
Lead Temperature Range (Soldering 60 sec) ....... +300°C
128-pin PLCC package: 8,A =100°C/W;
24-pin cerdip package: 0” =SS°C/W.
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied, Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
CONNECTION DIAGRAMS
24-Pin Cerdip Package
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'ELECT "IW' - FeGATTVE
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F roam:
GAIN art E n Iurmt a 0mm
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INPUT run OUTPUT
acumen " nscwitns
NEGAI’IV! " -
rosmvt E 0
OUTPUT
" NEGATIVE
cnmon Output
m ' " rosmv:
- n NEGATIVE
Logic Assignments Bit 0 Bit 1
AGC Acquire O 0
AGC Hold 0 l
Gain Set 1 t)
Input Clamp 1 l
ORDERING GUIDE
Package
Model Package Options'
AD89OJQ 24-Pin Cerdip Q-24
AD89OJP 28-Pin PLCC P-28A
*See Section 20 for package outline information.
28-Pin PLCC Package
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MASS STORAGE COMPONENTS 9-9
GAIN - (18
Typical Characteristics @ +25°c with :5 ll Supplies
vs 31.0
" 30.5
rosrnvzsumv
5 30.0
E t / 29.5
E 'i g
E g " / El 290
D > / g
2 t, /
d I' -to f 215
m -15 23.0
NEGAtWESUP8Y -20 2,45
-25 210
-60 -otr -m tt 20 " 60 " too 12tt "tt -M -40 -20 o " 40 so " too 120 no -60 40 -20 D 20 4o 60 m 100 120 tM
TEMPERATURe-= TEMPERATURE-t TEMPERATURE-T
Figure 1. Supply Current VS. Figure 2. Rectifier Offset vs. Figure 3. VGA Gain vs.
Temperature Temperature Temperature
100 " o
ii s... g
g g -tli
i’ " , " "ss, 'c, -ttt
E ' 's, a .
F- = 's, .., -MPC
g J, I -25 I l
E Le l
a g " 's, g "N nzs-c
"s, ~30
-35 701:
100k 1M 10M 100M , " 100 0 I00 zoo 300 are soo 600 no 000
FREQUENCV - Hz FREOUeNCr- MN: CONTROL VOLTAGE - mV
Figure 4. VGA Output Impedance Figure 5. VGA Voltage Noise vs. Figure tr. VGA Gain Reduction vs.
vs. Frequency Frequency Control Voltage
" 80 " 4-0
12.75 'N,
j 7" 's 3.2
12.70 / n 2.8
g 72 g
12.65 l' 24
2 's,, w
l " Q 2.0
12.50 23 m
o o 1.5
2 i, O
12.55 l "ss, 1.2
ttSO "
12.45 5.4 o
-60 -40 ~20 0 " 40 " " ‘00 120 140 , " 100
TEMPERATURE - 'C FREQUENCY- In":
Figure 7. X4 Buffer Gain vs.
Temperature
Figure 8. X4 Buffer Voltage Noise
vs. Frequency
9-10 MASS STORAGE COMPONENTS
-60 -60 -20 0 " " 60
TEMPERATURE-T
Figure 9. Hold-Mode Droop
Rate vs. Temperature
M 100 120 140
Applying the A0890
GENERAL LAYOUT REQUIREMENTS
Almost 60 dB of total gain is available at 100 MHz. Care must
be taken to ensure good RF practice in the PC layout to avoid
oscillations in the 150 MHz-350 MHz region. A parallel combi-
nation of 0.1 pF and 0.01 WF ceramic bypass capacitors should
be used as close to the supply pins as possible.
Additionally, a single pole RC filter applied at the input of each
stage, with a cutoff in the region of 100 MHz--150 MHz, will
help avoid oscillation problems. As a general rule, keep the con-
nections to interstage components as short as possible; it is also
recommended that any low pass filtering function which may be
required by the system be performed between the VGA stage
and the first X4 buffer amplifier. A ground plane should be
used to surround any interstage components wherever possible.
If these simple rules are followed, stable operation should be
assured.
BIASING THE RF GAIN STAGES
The VGA Stage
The 30 dB variable gain stage is biased at a potential of one di-
ode drop above analog ground. No additional dc bias is re-
quired, but ac coupling is necessary. The bias voltage is
maintained during normal operation and during operation of the
clamp. In order for the clamp to operate correctly with an emit-
ter follower driven input, 50 ft-loo n resistors should be placed
in series with the input coupling capacitors. These resistors can
be used in conjunction with a 5.1 pF shunt capacitor to limit
the input bandwidth to 150 MHz. in the case of an open collec-
tor driven input with resistive termination, no additional series
resistors are required.
The differential outputs have a nominal dc value of 1.5 V less
than the positive supply. Internal 1300 n resistors provide bias
current to the output emitter followers which operate with
2.7 mA nominal current. Output drive can be increased by an
additional 2.5 mA by paralleling external resistors to either the
analog ground or the negative power supply. However, caution
should be exercised in order to avoid causing excess dissipation
for the package. The recommended output level for the VGA is
300 mV p-p differential into 200 fl loads.
The X4 Buffers
The inputs of these stages have no committed dc biasing, and an
input bias current path must be provided. This path can nor-
mally be supplied via shunt resistors to analog ground which are
generally part of the interstage filter termination networks. The
inputs can be biased successfully within t 1.5 V of analog
ground.
Output drive can be increased in a similar manner to that de-
scribed for the VGA stage. The nominal dc output level is 2.5 V
with the internal 500 n load resistors connected to analog
ground which provides a nominal standing current of 5 mA to
the output emitter followers. This current can be increased by
up to an additional 5 mA by paralleling external resistors to ei-
ther analog ground or the negative power supply. As before,
precautions to limit excessive overall power dissipation apply
when steps are taken to increase the output drive capability.
1M 10M 100M u:
FREQUENCY - Hg
Figure 10. X4 Buffer Frequency Response (100 f
in Series with 1 p.F Load)
OPERATING THE FULL WAVE RECTIFIERS
The full wave rectifiers consist of two nearly identical stages.
Full wave rectification is performed in each stage using two
transistors whose emitters are connected together. The inputs to
the two full wave rectifiers are biased at one diode drop above
analog ground; therefore, ac coupling is recommended. The
full wave rectifier outputs - "AGC Rectifier" and "Qualifier
Threshold" - are connected directly to these commoned emit-
ters. Thus, the normal output voltage with zero input signal ap-
plied is close to analog ground. The "AGC Rectifier" pin allows
access to the output of the rectifier which drives the AGC
sample-and-hold section of the AD890. The "Qualifier
Threshold" pin allows access to the output of the threshold
rectifier.
The AGC rectifier has an internal 2 KO resistive pull-down con-
nected between analog ground and the negative power supply
pin. The threshold line has no built in pull-down, in order to
allow for a peak hold capability during thresholding. If a well
controlled rectifier offset is required, an external 4 kn pull-
down resistor at the "Qualifier Threshold" pin is recommended
and will produce a nominal 10 mV offset.
THE AGC SAMPLE-AND-HOLD
The AGC sample-and-hold section performs averaging of the
input waveform to set the RF average output level to 200 mV
single ended, or 330 mV peak for a sinusoidal signal. Thus,
without a peak hold capacitor at the "AGC Rectifier" pin, accu-
rate AGC operation only occurs with sinusoidal input signals.
An approximate 2 mA pull-down current is permanently present
at the "AGC Rectifier" pin, and a capacitor may be added here
to provide a degree of peak hold for AGC operation within non-
sinusoidal fields. A capacitance value of less than 0.03 ptF or
less per p.s of transition spacing is recommended. The addition
of the capacitor alters the symmetry of the attack and decay
rates of the rectifier, which is otherwise symmetric in operation.
In order to ensure that the overall AGC response is the same for
both high-to-low and low-to-high input level steps, it is neces-
sary to make the rectifier attack and decay times at least a factor
of two less than the AGC response time.
MASS STORAGE COMPONENTS 9-11
