AD8802AN ,12 Channel, 8-Bit TrimDACs with Power ShutdownCHARACTERISTICSInput Clock Pulse Width t , t Clock Level High or Low 15 nsCH CLData Setup Time t 5n ..
AD8802AN ,12 Channel, 8-Bit TrimDACs with Power ShutdownSpecifications apply to all DACsResolution N 8 BitsDifferential Nonlinearity Error DNL Guaranteed M ..
AD8802AR ,12 Channel, 8-Bit TrimDACs with Power ShutdownGENERAL DESCRIPTIONGND VRSREFLThe 12-channel AD8802/AD8804 provides independent digitally-(AD8802 O ..
AD8802ARU ,12 Channel, 8-Bit TrimDACs with Power ShutdownAPPLICATIONSO9REGAutomatic Adjustment O10SDI DD0O11Trimmer ReplacementD7 DACO1212Video and Audio Eq ..
AD8803 ,Octal 8-Bit TrimDAC with Power Shutdown & Mid-Scale Presetapplications ideallyallel shift register that is loaded from a standard three-wire serialsuited for ..
AD8803AR ,Octal 8-Bit TrimDAC with Power ShutdownSpecifications Apply to All DACsResolution N 8 BitsIntegral Nonlinearity Error INL –1.5 ±1/2 +1.5 ..
ADS2807Y/250G4 ,12-Bit, 50 MSPS Dual ADC, Int/Ext Ref., program. input range w/Out of Range Flg 64-HTQFP ELECTRICAL CHARACTERISTICS (Cont.)At T = full specified temperature range, V = +5V, differential in ..
ADS4146IRGZR ,14 bit 160MSPS Low Power ADC 48-VQFN -40 to 85MAXIMUM RATINGSOver operating free-air temperature range, unless otherwise noted.VALUE UNITSupply v ..
ADS4146IRGZT ,14 bit 160MSPS Low Power ADC 48-VQFN -40 to 85FEATURES DESCRIPTION23• Maximum Sample Rate: 250MSPSThe ADS412x/4x are a family of 12-bit/14-bit• U ..
ADS4149IRGZR ,14 bit 250MSPS Low Power ADC 48-VQFN -40 to 85FEATURES DESCRIPTION23• Maximum Sample Rate: 250MSPSThe ADS412x/4x are a family of 12-bit/14-bit• U ..
ADS4149IRGZT ,14 bit 250MSPS Low Power ADC 48-VQFN -40 to 85.(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green ..
ADS4149IRGZT ,14 bit 250MSPS Low Power ADC 48-VQFN -40 to 85MAXIMUM RATINGSOver operating free-air temperature range, unless otherwise noted.VALUE UNITSupply v ..
AD8802AN-AD8802AR-AD8802ARU-AD8804AN-AD8804AR-AD8804ARU
12 Channel, 8-Bit TrimDACs with Power Shutdown
FUNCTIONAL BLOCK DIAGRAM
CLK
SDI
SHDN
VDD
O10
O11
O12
VREFH
GNDRS
(AD8802 ONLY)
VREFL
(AD8804 ONLY)REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
12 Channel, 8-Bit TrimDACs
with Power Shutdown© Analog Devices, Inc., 1995
GENERAL DESCRIPTIONThe 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55mWatts Including IDD & IREF
Midscale Preset, AD8802
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated EquipmentEach DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 μA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 μA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1mm thin TSSOP-20
package.
NOTESTypicals represent average readings at +25°C.VREFH can be any value between GND and VDD, for the AD8804 VREFL can be any value between GND and VDD.Guaranteed by design and not subject to production test.Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz).See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
AD8802/AD8804–SPECIFICATIONS
(VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –408C≤TA ≤ +858C unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA,
SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
AD8802 PIN DESCRIPTIONS
PIN CONFIGURATIONS
AD8804 PIN DESCRIPTIONS
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
AD8802/AD8804–Typical Performance Characteristics
CODE – Decimal
INL – LSB
0.25256326496128160192224Figure 1.INL vs. Code
CODE – Decimal
INL – LSB
0.25256326496128160192224Figure 2.Differential Nonlinearity Error vs. Code
FREQUENCY
ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB
12800.20.40.60.81.0Figure 3.Total Unadjusted Error Histogram
CODE – Decimal
IREF
CURRENT – µAFigure 4.Input Reference Current vs. Code
10k
TEMPERATURE – °C
SHUTDOWN CURRENT – nAFigure 5.Shutdown Current vs. Temperature
Figure 6.Supply Current vs. Temperature
INPUT VOLTAGE – Volts34.543.5
SUPPLY CURRENT – mAFigure 7.Supply Current vs. Logic Input Voltage
100100k10k1k10
FREQUENCY – Hz
PSRR – dBFigure 8.Power Supply Rejection vs. Frequency
TIME – 5µs/DIV
OUT Figure 9.Large-Signal Settling Time
TIME – 0.2µs/DIV
OUTPUT2 – 10mV/DIVFigure 10.Adjacent Channel Clock Feedthrough
Figure 11.Midscale Transition
HOURS OF OPERATION AT 150°C
CHANGE IN ZERO-SCALE ERROR – LSB
200400Figure 12.Zero-Scale Error Accelerated by Burn-In
AD8802/AD8804
HOURS OF OPERATION AT 150°C
CHANGE IN FULL-SCALE ERROR – LSB
100400Figure 13.Full-Scale Error Accelerated by Burn-In
Figure 14.REF Input Resistance Accelerated by Burn-In
OPERATIONThe AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC# = A3 × 8 + A2 × 4 + A1 × 2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6μs (13 × 12 ×ns). The exact timing requirements are shown in Figure 15.
Table I.Serial-Data Word FormatThe AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and VREF inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
+5V
SDI
CLK
VOUTFigure 15a.Timing Diagram
Figure 15b.Detail Timing Diagram
±1 LSB ERROR BAND
+5V
2.5V
VOUT
RESET TIMINGFigure 15c.Reset Timing Diagram
PROGRAMMING THE OUTPUT VOLTAGEThe output voltage range is determined by the external refer-
ence connected to VREFH and VREFL pins. See Figure 16 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8802 its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation which determines the programmed output
voltage is:
VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFLEq. 1
where Dx is the data contained in the 8-bit DACx register.
TO OTHER DACSGND
VREFL
VREFH...
Figure 16.AD8802/AD8804 Equivalent TrimDAC Circuit
For example, when VREFH = +5 V and VREFL = 0 V, the follow-
ing output voltages will be generated for the following codes:
REFERENCE INPUTS (VREFH, VREFL)The reference input pins set the output voltage range of all
twelve DACs. In the case of the AD8802 only the VREFH pin is
available to establish a user designed full-scale output voltage.
The external reference voltage can be any value between 0 and
VDD but must not exceed the VDD supply voltage. The AD8804
has access to the VREFL which establishes the zero-scale output
voltage, any voltage can be applied between 0 V and VDD. VREFL
can be smaller or larger in voltage than VREFH since the DAC
design uses fully bidirectional switches as shown in Figure 16.
The input resistance to the DAC has a code dependent variation
which has a nominal worst case measured at 55H, which is ap-
proximately 1.2kΩ. When VREFH is greater than VREFL, the
ladder, while the REFH reference is sourcing current into the
DAC ladder. The DAC design minimizes reference glitch cur-
rent maintaining minimum interference between DAC channels
during code changes.
DAC OUTPUTS (O1–O12)The twelve DAC outputs present a constant output resistance of
approximately 5kΩ independent of code setting. The distribu-
tion of ROUT from DAC-to-DAC typically matches within ±1%.
However device-to-device matching is process lot dependent
having a ±20% variation. The change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all twelve outputs are open-circuited.
Figure 17.Block Diagram
DIGITAL INTERFACINGThe AD8802/AD8804 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 17 block diagram shows more detail of the internal digital
circuitry. When CS is taken active low, the clock can load data
into the serial register on each positive clock edge, see Table II.
Table II.Input Logic Control Truth TableP = Positive Edge, X = Don’t Care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the twelve positive-edge triggered
AD8802/AD8804..
DAC 12
CLK
SDI
DAC 2
DAC 1Figure 18.Equivalent Control Logic
The target DAC register is loaded with the last eight bits of the
serial data-word completing one DAC update. Twelve separate
12-bit data words must be clocked in to change all twelve out-
put settings.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 19. Applies to
digital input pins CS, SDI, RS, SHDN, CLK
Figure 19.Equivalent ESD Protection Circuit
Digital inputs can be driven by voltages exceeding the AD8802/
AD8804 VDD supply value. This allows 5 V logic to interface
directly to the part when it is operated at 3 V.
APPLICATIONS
Supply BypassingPrecision analog products, such as the AD8802/AD8804, re-
quire a well filtered power source. Since the AD8802/AD8804
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
If possible, the AD8802/AD8804 should be powered directly
from the system power supply. This arrangement, shown in Fig-
ure 20, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 μF tan-
talum electrolytic in parallel with a 0.1 μF ceramic capacitor is
recommended (Figure 21).
Figure 20.Use Separate Traces to Reduce Power Supply
Noise
Figure 21.Recommended Supply Bypassing for the
AD8802/AD8804
Buffering the AD8802/AD8804 OutputIn many cases, the nominal 5 kΩ output impedance of the
AD8802/AD8804 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 22. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
The next two DACs, B and C, are configured in a summing
arrangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
+5V
DIGITAL INTERFACING
OMITTED FOR CLARITY
SIMPLE BUFFER
0V TO 5V
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENTFigure 22.Buffering the AD8802/AD8804 Output
Increasing Output Voltage SwingAn external amplifier can also be used to extend the output volt-
age swing beyond the power supply rails of the AD8802/AD8804.
This technique permits an easy digital interface for the DAC,
while expanding the output swing to take advantage of higher
voltage external power supplies. For example, DAC A of Fig-
ure 23 is configured to swing from –5 V to +5 V. The actual
output voltage is given by:
VOUT=1+RRS×D
256×5V()±5V
where D is the DAC input value (i.e., 0 to 255). This circuit can
be combined with the “fine/coarse” circuit of Figure 22 if, for
example, a very accurate adjustment around 0 V is desired.
