AD8801AN-AD8801AR-AD8803AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD8801AR ,Octal 8-Bit TrimDAC with Power Shutdownapplications ideallyallel shift register that is loaded from a standard three-wire serialsuited for ..
AD8801ARZ , Octal 8-Bit TrimDAC with Power Shutdown
AD8802AN ,12 Channel, 8-Bit TrimDACs with Power ShutdownCHARACTERISTICSInput Clock Pulse Width t , t Clock Level High or Low 15 nsCH CLData Setup Time t 5n ..
AD8802AN ,12 Channel, 8-Bit TrimDACs with Power ShutdownSpecifications apply to all DACsResolution N 8 BitsDifferential Nonlinearity Error DNL Guaranteed M ..
AD8802AR ,12 Channel, 8-Bit TrimDACs with Power ShutdownGENERAL DESCRIPTIONGND VRSREFLThe 12-channel AD8802/AD8804 provides independent digitally-(AD8802 O ..
AD8802ARU ,12 Channel, 8-Bit TrimDACs with Power ShutdownAPPLICATIONSO9REGAutomatic Adjustment O10SDI DD0O11Trimmer ReplacementD7 DACO1212Video and Audio Eq ..
ADS2807Y/250 ,12-Bit, 50 MSPS Dual ADC, Int/Ext Ref., program. input range w/Out of Range FlgTIMING DIAGRAMN + 2N + 1N + 4N + 3Analog In N + 7N + 5NN + 6t tL Ht tD CONVClock6 Clock Cyclest2Dat ..
ADS2807Y/250G4 ,12-Bit, 50 MSPS Dual ADC, Int/Ext Ref., program. input range w/Out of Range Flg 64-HTQFP ELECTRICAL CHARACTERISTICS (Cont.)At T = full specified temperature range, V = +5V, differential in ..
ADS4146IRGZR ,14 bit 160MSPS Low Power ADC 48-VQFN -40 to 85MAXIMUM RATINGSOver operating free-air temperature range, unless otherwise noted.VALUE UNITSupply v ..
ADS4146IRGZT ,14 bit 160MSPS Low Power ADC 48-VQFN -40 to 85FEATURES DESCRIPTION23• Maximum Sample Rate: 250MSPSThe ADS412x/4x are a family of 12-bit/14-bit• U ..
ADS4149IRGZR ,14 bit 250MSPS Low Power ADC 48-VQFN -40 to 85FEATURES DESCRIPTION23• Maximum Sample Rate: 250MSPSThe ADS412x/4x are a family of 12-bit/14-bit• U ..
ADS4149IRGZT ,14 bit 250MSPS Low Power ADC 48-VQFN -40 to 85.(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green ..

AD8801AN-AD8801AR-AD8803AR
Octal 8-Bit TrimDAC with Power Shutdown
REV.AOctal 8-Bit TrimDAC
with Power Shutdown
FEATURES
Low Cost
Replaces Eight Potentiometers
Eight Individually Programmable Outputs
Three-Wire Serial Input
Power Shutdown ≤ 25 mW Including IDD and IREF
Midscale Preset, AD8801
Separate VREFL Range Setting, AD8803
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Potentiometer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The AD8801/AD8803 provides eight digitally controlled dc
voltage outputs. This potentiometer divider TrimDAC® allows
replacement of the mechanical trimmer function in new designs.
The AD8801/AD8803 is ideal for dc voltage adjustment
applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8801 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8803 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of de-
vices with a limited allowable voltage control range.
FUNCTIONAL BLOCK DIAGRAM
(DACs 2–7 Omitted for Clarity)
Internally the AD8801/AD8803 contain eight voltage output
digital-to-analog converters, sharing a common reference volt-
age input.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-par-
allel shift register that is loaded from a standard three-wire serial
input digital interface. Eleven data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 3 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. The AD8801/AD8803
consumes only 5 μA from 5 V power supplies. In addition, in
shutdown mode reference input current consumption is also re-
duced to 5 μA while saving the DAC latch settings for use after
return to normal operation.
The AD8801/AD8803 is available in 16-pin plastic DIP and the
1.5 mm height SO-16 surface mount packages.
TrimDAC is a registered trademark of Analog Devices, Inc.
See the AD8802/AD8804 for a twelve channel version of this product.
NOTESTypical values represent average readings measured at +25°C.VREFH can be any value between GND and VDD, for the AD8803 VREFL can be any value between GND and VDD.Guaranteed by design and not subject to production test.Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
AD8801/AD8803–SPECIFICATIONS
(VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –408C
≤ TA ≤ +858C unless otherwise noted)
ORDERING GUIDE
AD8803 PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3, +8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . .0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . .0 V, VDD
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . .(TJ MAX – TA)/θJA
Thermal Resistance θJA,
SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60°C/W
P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57°C/W
AD8801 PIN DESCRIPTIONS
PIN CONFIGURATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
AD8801/AD8803
+5V
SDI
CLK
VOUT
OCTAL 8-BIT TRIMDAC, WITH SHUTDOWN
Figure 2a.Timing Diagram
+5V
SDI
(DATA
IN)
CLK
VOUT
±1 LSB ERROR BAND
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
Figure 2b.Detail Timing Diagram
±1 LSB ERROR BAND
+5V
2.5V
VOUT
RESET TIMING
Figure 2c.Reset Timing Diagram
Table I.Serial-Data Word Format
OPERATION
The AD8801/AD8803 provides eight channels of programmable
voltage output adjustment capability. Changing the programmed
output voltage of each TrimDAC is accomplished by clocking in
an 11-bit serial data word into the SDI (Serial Data Input) pin.
The format of this data word is three address bits, MSB first,
followed by eight data bits, MSB first. Table I provides the se-
rial register data word format. The AD8801/AD8803 has the
following address assignments for the ADDR decode which de-
termines the location of DAC register receiving the serial regis-
ter data in bits B7 through B0:
DAC # = A2 × 4 + A1 × 2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it possible
to load all eight DACs in as little time as 3 μs (12 × 8 × 30 ns).
The exact timing requirements are shown in Figure 2.
The AD8801 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power up. The
AD8803 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN that places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply,
VREF inputs, and all 8 outputs. In shutdown mode the DACx
latch settings are maintained. When returning to operational
mode from power shutdown the DAC outputs return to their
previous voltage settings.
TO OTHER DACS..
GND
VREFL
VREFH
Figure 3.AD8801/AD8803 Equivalent TrimDAC Circuit
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to VREFH and VREFL pins. See Figure 3 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8801, its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation that determines the programmed output
voltage is:
VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL (1)
where Dx is the data contained in the 8-bit DACx latch.
For example, when VREFH = +5 V and VREFL = 0 V the follow-
ing output voltages will be generated for the following codes:
REFERENCE INPUTS (VREFH, VREFL)
The reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the VREFH pin is avail-
able to establish a user designed full-scale output voltage. The
external reference voltage can be any value between 0 and VDD
but must not exceed the VDD supply voltage. In the case of the
AD8803, which has access to the VREFL which establishes the
zero-scale output voltage, any voltage can be applied between
0 V and VDD. VREFL can be smaller or larger in voltage than
VREFH since the DAC design uses fully bidirectional switches as
shown in Figure 3. The input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55H, which is approximately 2 kΩ. When VREFH is greater than
VREFL, the REFL reference must be able to sink current out of
the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. The DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.
DAC OUTPUTS (O1–O8)
The eight DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. The distribu-
tion of ROUT from DAC to DAC typically matches within ±1%.
However, device to device matching is process lot dependent
having a ±20% variation. The change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all eight outputs are open circuited.
VDD
VREFH
CLK
SDI
SHDN
DIGITAL INTERFACING
The AD8801/AD8803 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 4 block diagram shows more detail of the internal digital cir-
cuitry. When CS is taken active low, the clock can load data into
the serial register on each positive clock edge, see Table II.
Table II. Input Logic Control Truth Table
NOTE: P = positive edge, X = don’t care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail...
DAC 1
DAC 2
DAC 8
CLK
SDI
Figure 5.Equivalent Control Logic
The target DAC register is loaded with the last eight bits of the se-
rial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. This applies to
digital input pins CS, SDI, RS, SHDN, CLK.
Figure 6.Equivalent ESD Protection Circuit
Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 VDD value. This allows 5 V logic to interface directly to
the part when it is operated at 3 V.
CODE – Decimal
INL – LSB0256326496128160192224
0.25
Figure 7.INL vs. Code
CODE – Decimal
DNL – LSB025664128192
0.25
Figure 8.Differential Nonlinearity Error vs. Code
FREQUENCY
TOTAL UNADJUSTED ERROR – LSB
120
Figure 9.Total Unadjusted Error Histogram
CODE – Decimal
IREF
CURRENT – µA96128160192224
150
Figure 10.Input Reference Current vs. Code
10k
TEMPERATURE – °C1251058545
IREF
SHUTDOWN CURRENT – nA
Figure 11.Shutdown Current vs. Temperature
Figure 12.Supply Current vs. Temperature
AD8801/AD8803–Typical Performance Characteristics
LOGIC INPUT VOLTAGE – Volts34.543.5
IDD
SUPPLY CURRENT – mA
Figure 13.Supply Current vs. Logic Input Voltage
100100k10k1k10
FREQUENCY – Hz
PSRR – dB
Figure 14.Power Supply Rejection vs. Frequency
TIME – 1µs/DIV
OUT1
Figure 15.Large-Signal Settling Time
Figure 16.Adjacent Channel Clock Feedthrough
Figure 17.Midscale Transition
HOURS OF OPERATION AT 150°C
CHANGE IN ZERO-SCALE ERROR – LSB
0.005
Figure 18.Zero-Scale Error Accelerated by Burn-In
AD8801/AD8803
HOURS OF OPERATION AT 150°C
CHANGE IN FULL-SCALE ERROR – LSB
Figure 19.Full-Scale Error Accelerated by Burn-In
HOURS OF OPERATION AT 150°C
INPUT RESISTANCE DRIFT – k
0.5
Figure 20.REF Input Resistance Accelerated by Burn-In
Figure 22.Recommended Supply Bypassing for the
AD8801/AD8803
Buffering the AD8801/AD8803 Output
In many cases, the nominal 5 kΩ output impedance of the
AD8801/AD8803 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 23. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
The next two DACs, B and C, are configured in a summing ar-
rangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
APPLICATIONS
Supply Bypassing
Precision analog products, such as the AD8801/AD8803, re-
quire a well filtered power source. Since the AD8801/AD8803
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
If possible, the AD8801/AD8803 should be powered directly
from the system power supply. This arrangement, shown in Fig-
ure 21, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 μF tan-
talum electrolytic in parallel with a 0.1 μF ceramic capacitor is
recommended (Figure 22).
Figure 21.Use Separate Traces to Reduce Power Supply
Noise

Partno	Mfg	Dc	Qty	Available	Descript
AD8801AN	AD	N/a	20	avai	Octal 8-Bit TrimDAC with Power Shutdown
AD8801AR	AD	N/a	1319	avai	Octal 8-Bit TrimDAC with Power Shutdown
AD8803AR	AD	N/a	18	avai	Octal 8-Bit TrimDAC with Power Shutdown