AD876JR-AD876JR-8-AD876JRS Fast Delivery |IC PHOENIX CO.,LIMITED

AD876JR ,10-Bit 20 MSPS 160 mW CMOS A/D ConverterSpecifications subject to change without notice. See Definition of
AD876JR-8 ,10-Bit 20 MSPS 160 mW CMOS A/D Converterapplications. Its speed and reso- The AD876 offers three-state output control.lution ideally suit ..
AD876JRS ,10-Bit 20 MSPS 160 mW CMOS A/D ConverterSpecifications for additional information.–2– REV. BAD876(T to T with AV = +5.0 V, DV = +5.0 V, DRV ..
AD876JRS ,10-Bit 20 MSPS 160 mW CMOS A/D ConverterFEATURESFUNCTIONAL BLOCK DIAGRAMCMOS 10-Bit 20 MSPS Sampling A/D ConverterPin-Compatible 8-Bit Opti ..
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ADS2806Y/250 ,12-Bit, 32 MSPS Dual ADC, Int/Ext Ref., program. input range w/Out of Range FlagFEATURESAPPLICATIONS* SPURIOUS-FREE DYNAMIC RANGE:* COMMUNICATIONS IF PROCESSING73dB at 10MHz fIN* ..
ADS2807Y/250 ,12-Bit, 50 MSPS Dual ADC, Int/Ext Ref., program. input range w/Out of Range FlgTIMING DIAGRAMN + 2N + 1N + 4N + 3Analog In N + 7N + 5NN + 6t tL Ht tD CONVClock6 Clock Cyclest2Dat ..
ADS2807Y/250G4 ,12-Bit, 50 MSPS Dual ADC, Int/Ext Ref., program. input range w/Out of Range Flg 64-HTQFP ELECTRICAL CHARACTERISTICS (Cont.)At T = full specified temperature range, V = +5V, differential in ..
ADS4146IRGZR ,14 bit 160MSPS Low Power ADC 48-VQFN -40 to 85MAXIMUM RATINGSOver operating free-air temperature range, unless otherwise noted.VALUE UNITSupply v ..
ADS4146IRGZT ,14 bit 160MSPS Low Power ADC 48-VQFN -40 to 85FEATURES DESCRIPTION23• Maximum Sample Rate: 250MSPSThe ADS412x/4x are a family of 12-bit/14-bit• U ..

AD876JR-AD876JR-8-AD876JRS
10-Bit 20 MSPS 160 mW CMOS A/D Converter
REV.B10-Bit 20 MSPS 160 mW
CMOS A/D Converter
FEATURES
CMOS 10-Bit 20 MSPS Sampling A/D Converter
Pin-Compatible 8-Bit Option
Power Dissipation: 160 mW
+5 V Single Supply Operation
Differential Nonlinearity: 0.5 LSB
Guaranteed No Missing Codes
Power Down (Standby) Mode
Three-State Outputs
Digital I/Os Compatible with +5 V or +3.3 V Logic
Adjustable Reference Input
Small Size: 28-Lead SOIC, 28-Lead SSOP, or 48-Lead
Thin Quad Flatpack (TQFP)
PRODUCT DESCRIPTION
The AD876 is a CMOS, 160 mW, 10-bit, 20 MSPS analog-to-
digital converter (ADC). The AD876 has an on-chip input
sample-and-hold amplifier. By implementing a multistage pipe-
lined architecture with output error correction logic, the AD876
offers accurate performance and guarantees no missing codes
over the full operating temperature range. Force and sense con-
nections to the reference inputs minimize external voltage drops.
The AD876 can be placed into a standby mode of operation
reducing the power below 50 mW. The AD876’s digital I/O
interfaces to either +5 V or +3.3 V logic. Digital output pins
can be placed in a high impedance state; the format of the out-
put is straight binary coding.
The AD876’s speed, resolution and single-supply operation
ideally suit a variety of applications in video, multimedia, imag-
ing, high speed data acquisition and communications. The
AD876’s low power and single-supply operation satisfy require-
ments for high speed portable applications. Its speed and reso-
lution ideally suit charge coupled device (CCD) input systems
such as color scanners, digital copiers, electronic still cameras
and camcorders.
The AD876 comes in a space saving 28-lead SOIC and 48-lead
thin quad flatpack (TQFP) and is specified over the commercial
(0°C to +70°C) temperature range.
PRODUCT HIGHLIGHTS
Low Power
The AD876 at 160 mW consumes a fraction of the power of
presently available 8- or 10-bit, video speed converters. Power-
down mode and single-supply operation further enhance its
desirability in low power, battery operated applications such
as electronic still cameras, camcorders and communication
systems.
Very Small Package
The AD876 comes in a 28-lead SOIC, 28-lead SSOP, and 48-
lead surface mount, thin quad flat package. The TQFP package
is ideal for very tight, low headroom designs.
Digital I/O Functionality
The AD876 offers three-state output control.
Pin Compatible Upgrade Path
The AD876 offers the option of laying out designs for eight
bits and migrating to 10-bit resolution if prototype results
warrant.
FUNCTIONAL BLOCK DIAGRAM
AD876–SPECIFICATIONS
ANALOG INPUT
REFERENCE INPUT
DYNAMIC PERFORMANCE
POWER SUPPLIES
NOTESAVDD and DVDD must be within 0.5 V of each other to maintain specified performance levels.3.58 MHz Input Frequency.
Specifications subject to change without notice. See Definition of Specifications for additional information.
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +3.3 V, VREFB = +4.0 V, VREFB =
+2.0 V, fCLOCK = 20 MSPS, unless otherwise noted)
DIGITAL SPECIFICATIONS
LOGIC OUTPUTS
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Maximum Conversion Rate
Clock High
NOTEConversion rate is operational down to 10 kHz without degradation in specified performance.
Figure 1.Timing Diagram
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +3.3 V, VREFT = +4.0 V, VREFB = +2.0 V,
fCLOCK = 20 MSPS, CL = 20 pF unless otherwise noted)
AD876
STATE
STBY
CLK
CML
REFTF
REFBF
REFTS
REFBS
AIN
AVDD
AVSS
DVDD
DVSS
DRVDD
DRVSS
Type:AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power.
PIN CONFIGURATIONS
SOIC/SSOP TQFP
PIN FUNCTION DESCRIPTIONS
PINS D0 AND D1 ARE LEFT OPEN
FOR THE AD876JR-8
AVSS
DRVDD
AVDD
AIN
REFBF
REFTF
*D0
*D1
CML
REFBSREFTSDVSSDVSSDVDDSTBY
DRVSSTHREE-STATE
DVSSCLK
NC = NO CONNECT
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Figure 2.Equivalent Circuits
REFTF
REFTS
REFBS
REFBF
AVDD
AVDD
AVSS
AVDD
AVDD
AVSS
INTERNAL
REFERENCE
VOLTAGE
INTERNAL
REFERENCE
VOLTAGE
DRVDD
DVSS
DRVSS
DVDD
DRVDD
DRVSS
DVSS
DVDD
AVDD
AVSS
DRVDD
DRVSSDVSS
DVDD
c) CLK
d) AIN
a) D0–D9b) Three-State, Standby
AD876
Figure 3.AD876 Typical DNL
FREQUENCY – MHz
GAIN – dB
Figure 4.Full Power Bandwidth
INPUT FREQUENCY – MHz
Figure 5.SINAD vs. Input Frequency
(fCLK = 20 MSPS, AIN = –0.5 dB)
FREQUENCY – MHz
–90
Figure 6.THD vs. Input Frequency 2nd, 3rd Harmonics
CLOCK FREQUENCY – MHz53010152025
Figure 7.SINAD vs. CLK Frequency (AIN = –0.5 dB)
CLOCK FREQUENCY – MHz
100
Figure 8.Power Consumption vs. Sample Rate
–Typical Performance Characteristics
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale”. The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
OFFSET ERROR
The first transition should occur at a level 1/2 LSB above
“zero.” Offset is defined as the deviation of the actual first code
transition from that point.
GAIN ERROR
The first code transition should occur for an analog value 1/2 LSB
above nominal negative full scale. The last transition should
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
REFERENCE TOP/BOTTOM OFFSET
Resistance between the reference input and comparator input
tap points causes offset errors. These errors can be nulled out
by using the force-sense connection as shown in the Reference
Input section.
THEORY OF OPERATION
The AD876 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD876 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD876 requires a small fraction of the 1023
comparators used in a traditional flash type A/D. A sample-and-
hold function within each of the stages permits the first stage to
operate on a new input sample while the second and third stages
operate on the two preceding samples.
APPLYING THE AD876
DRIVING THE ANALOG INPUT
Figure 11 shows the equivalent analog input of the AD876, a
sample-and-hold amplifier (SHA). Bringing CLK to a logic low
level closes Switches 1 and 2 and opens Switch 3. The input
source connected to AIN must charge capacitor CH during this
time. When CLK transitions from logic “low” to logic “high,”
Switch 1 opens first, placing the SHA in hold mode. Switch 2
opens subsequently. Switch 3 then closes, connects the feed-
back loop around the op amp, and forces the output of the op
amp to equal the voltage stored on CH. When CLK transitions
from logic “high” to logic “low”, Switch 3 opens first. Switch 2
closes and reconnects the input to CH. Finally, Switch 1 closes
and places the SHA in track mode.
The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance,
CP, and the hold capacitance, CH, is typically less than 5 pF.
The input source must be able to charge or discharge this ca-
pacitance to 10-bit accuracy in one half of a clock cycle. When
the SHA goes into track mode, the input source must charge or
discharge capacitor CH from the voltage already stored on CH
(the previously captured sample) to the new voltage. In the
worst case, a full-scale voltage step on the input, the input
source must provide the charging current through the RON (50 Ω)
of Switch 2 and quickly settle (within 1/2 CLK period). This
situation corresponds to driving a low input impedance. On the
other hand, when the source voltage equals the value previously
stored on CH, the hold capacitor requires no input current and
the equivalent input impedance is extremely high.
Adding series resistance between the output of the source and
the AIN pin reduces the drive requirements placed on the
source. Figure 12 shows this configuration. The bandwidth of
the particular application limits the size of this resistor. To
maintain the performance outlined in the data sheet specifica-
Figure 9.AD876JR-8 Typical FFT (fIN = 3.58 MHz,
AIN = –0.5 dB, fCLOCK = 20 MSPS)
Figure 10.AD876 Typical FFT (fIN = 3.58 MHz, AIN = –0.5 dB,
fCLOCK = 20 MSPS)
AD876kHz. At a sample clock frequency of 20 MHz, the dc bias
current at 3 V dc is approximately 30 μA. If we choose R2 equal
to 1 kΩ and R1 equal to 50 Ω, the parallel capacitance should
be a minimum of 0.008 μF to avoid attenuating signals close to
20 kHz. Note that the bias current will cause a 31.5 mV offset
from the 3 V bias.
In systems that must use dc-coupling, use an op amp to level-
shift a ground-referenced signal to comply with the input
requirements of the AD876. Figure 14 shows an AD817
configured in inverting mode with ac signal gain of –1. The dc
voltage at the noninverting input of the op amp controls the
amount of dc level shifting. A resistive voltage divider attenu-
ates the REFBF signal. The op amp then multiplies the attenu-
ated signal by 2. In the case where REFBF = 1.6 V, the dc
output level will be 2.6 V. The AD817 is a low cost, fast settling,
single supply op amp with a G = –1 bandwidth of 29 MHz. The
AD818 is similar to the AD817 but has a 50 MHz bandwidth.
Other appropriate op amps include the AD8011, AD812 (a dual),
and the AD8001.
Figure 14. Bipolar Level Shift
An integrated difference amplifier such as the AD830 is an
alternate means of providing dc level shifting. The AD830
provides a great deal of flexibility with control over offset and
gain. Figure 15 shows the AD830 precisely level-shifting a
unipolar, ground-referenced signal. The reference voltage,
REFBS, determines the amount of level-shifting. The ac gain
is 1. The AD830 offers the advantages of high CMRR, precise
gain, offset, and high-impedance inputs when compared with a
discrete implementation. For more information regarding the
AD830, see the AD830 data sheet.
Figure 15. Level Shifting with the AD830
REFERENCE INPUT DRIVING THE REFERENCE
TERMINALS
The AD876 requires an external reference on pins REFTF and
analog ground can lower the ac source impedance. The value
of this capacitance will depend on the source resistance and the
required signal bandwidth.
The input span of the AD876 is a function of the reference
voltages. For more information regarding the input range, see
the DRIVING THE REFERENCE TERMINALS section of
the data sheet.
Figure 11.AD876 Equivalent Input Structure
Figure 12.Simple AD876 Drive Requirements
In many cases, particularly in single-supply operation, ac-
coupling offers a convenient way of biasing the analog input
signal at the proper signal range. Figure 13 shows a typical
configuration for ac-coupling the analog input signal to the
AD876. Maintaining the specifications outlined in the data
sheet requires careful selection of the component values. The
most important concern is the f-3 dB high-pass corner that is a
function of R2, and the parallel combination of C1 and C2.
The f-3 dB point can be approximated by the equation
where Ceq is the parallel combination of C1 and C2. Note that
C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Adding a small ceramic
or polystyrene capacitor on the order of 0.01 μF that does not
become inductive until negligibly higher frequencies maintains
a low impedance over a wide frequency range.
Figure 13.AC-Coupled Inputs
There are additional considerations when choosing the resistor
values. The ac-coupling capacitors integrate the switching
transients present at the input of the AD876 and cause a net dc
bias current, IB, to flow into the input. The magnitude of this
bias current increases with increasing dc signal level and also
increases with sample frequency. This bias current will result in
an offset error of (R1 + R2) × IB. If it is necessary to compen-

Partno	Mfg	Dc	Qty	Available	Descript
AD876JRS	AD	N/a	963	avai	10-Bit 20 MSPS 160 mW CMOS A/D Converter
AD876JR		N/a	7033	avai	10-Bit 20 MSPS 160 mW CMOS A/D Converter
AD876JR-8 \|AD876JR8	AD	N/a	11	avai	10-Bit 20 MSPS 160 mW CMOS A/D Converter
AD876JRS	ANALOG	N/a	19	avai	10-Bit 20 MSPS 160 mW CMOS A/D Converter