AD872ASD/883B Fast Delivery |IC PHOENIX CO.,LIMITED

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AD872ASD/883B
Complete 12-Bit 10 MSPS Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
REV.AComplete 12-Bit 10 MSPS
Monolithic A/D Converter
FEATURES
Monolithic 12-Bit 10 MSPS A/D Converter
Low Noise: 0.26 LSB RMS Referred-to-Input
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.5 LSB
Signal-to-Noise and Distortion Ratio: 68 dB
Spurious-Free Dynamic Range: 75 dB
Power Dissipation: 1.03 W
Complete: On-Chip Track-and-Hold Amplifier and
Voltage Reference
Twos Complement Binary Output Data
Out-of-Range Indicator
28-Lead Ceramic DIP or 44-Terminal Leadless Chip
Carrier Package
PRODUCT DESCRIPTION
The AD872A is a monolithic 12-bit, 10 MSPS analog-to-digital
converter with an on-chip, high performance track-and-hold
amplifier and voltage reference. The AD872A uses a multistage
differential pipelined architecture with error correction logic to
provide 12-bit accuracy at 10 MSPS data rates and guarantees
no missing codes over the full operating temperature range. The
AD872A is a redesigned version of the AD872 which has been
optimized for lower noise. The AD872A is pin compatible with
the AD872, allowing the parts to be used interchangeably as sys-
tem requirements change.
The low noise input track-and-hold (T/H) of the AD872A is
ideally suited for high-end imaging applications. In addition, the
T/H’s high input impedance and fast settling characteristics al-
low the AD872A to easily interface with multiplexed systems
that switch multiple signals through a single A/D converter. The
dynamic performance of the T/H also renders the AD872A suit-
able for sampling single channel inputs at frequencies up to and
beyond the Nyquist rate. The AD872A provides both reference
output and reference input pins, allowing the onboard reference
to serve as a system reference. An external reference can also be
chosen to suit the dc accuracy and temperature drift require-
ments of the application. A single clock input is used to control
all internal conversion cycles. The digital output data is pre-
sented in twos complement binary output format. An out-of-
range signal indicates an overflow condition, and can be used
with the most significant bit to determine low or high overflow.
The AD872A is fabricated on Analog Devices’ ABCMOS-l
process that utilizes high speed bipolar and CMOS transistors
on a single chip.
The AD872A is packaged in a 28-lead ceramic DIP and a 44-
terminal leadless ceramic surface mount package (LCC). Opera-
tion is specified from 0°C to +70°C and –55°C to +125°C.
PRODUCT HIGHLIGHTS
The AD872A offers a complete single-chip sampling, 12-bit
10 MSPS analog-to-digital conversion function in a 28-lead DIP
or 44-terminal LCC.
Low Noise—The AD872A features 0.26 LSB rms referred to-
input noise.
Low Power—The AD872A at 1.03 W consumes a fraction of the
power of presently available hybrids.
On-Chip Track-and-Hold (T/H)—The low noise, high imped-
ance T/H input eliminates the need for external buffers and can
be configured for single-ended or differential inputs.
Ease of Use—The AD872A is complete with T/H and voltage
reference and is pin-compatible with the AD872.
Out of Range (OTR)—The OTR output bit indicates when the
input signal is beyond the AD872A’s input range.
AD872A–SPECIFICATIONS
DC SPECIFICATIONS(TMIN to TMAX, AVDD = + 5 V, DVDD = +5 V, AVSS = –5 V, fSAMPLE = 10 MHz unless otherwise noted)
ANALOG INPUT
INTERNAL VOLTAGE REFERENCE
NOTESTemperature ranges are as follows: J Grade: 0°C to +70°C, S Grade: –55°C to +125°C.Adjustable to zero with external potentiometers (see Zero and Gain Error Calibration section).+25°C to TMIN and +25°C to TMAX.Includes internal voltage reference drift.Excludes internal voltage reference drift.Change in Gain Error as a function of the dc supply voltage (VNOMINAL to VMIN, VNOMINAL to VMAX).LCC package only.
Specifications subject to change without notice.
AC SPECIFICATIONS(TMIN to TMAX, AVDD = + 5 V, DVDD = +5 V, AVSS = –5 V, fSAMPLE = 10 MHz unless otherwise noted)1
AD872A
NOTESfINPUT amplitude = –0.5 dB full scale unless otherwise indicated. All measurements referred to a 0 dB (1.0 V pk) input signal unless otherwise indicated.fa = 1.0 MHz, fb = 0.95 MHz with tSAMPLE = 10 MHz.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = + 5 V, DVDD = +5 V, AVSS = –5 V, fSAMPLE = 10 MHz unless otherwise noted)
AD872A
SWITCHING SPECIFICATIONS
NOTESConversion rate is operational down to 10 kHz without degradation in specified performance.See section on Three-State Outputs for timing diagrams and applications information.
Specifications subject to change without notice.
CLOCK
N+1
VIN
tOD
BIT 2–12
MSB, OTR
Figure 1.Timing Diagram
ABSOLUTE MAXIMUM RATINGS1
AVSS
DVDD, DRVDD
Digital Outputs
VINA, VINB, REF IN
REF IN
Storage Temperature
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.LCC package only.
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V; VIL = 0.8 V,
VIN = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
PIN DESCRIPTION
VINB
AVSS
AVDD
AGND
DGND
DVDD
BIT 12 (LSB)
BIT 2–BIT 11
MSB
OTR
CLK
REF OUT
REF GND
REF IN
DRVDD
DRGND
OEN
TYPE:AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP. Only available on
44-terminal surface mount package.
PIN CONFIGURATIONS
28-Lead Ceramic DIP44-Terminal LCC
VINA
AVSS
REF OUT
REF GND
REF IN
VINB
AVSS
AVDD
DVDD
DGND
AGNDAGND
DGND
DVDD
BIT 12 (LSB)
BIT 11
BIT 10MSB
OTR
CLK
BIT 9
BIT 8
BIT 7
BIT 2
BIT 4
BIT 3
AD872A
DEFINITIONS OF SPECIFICATIONS
LINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs
1/2 LSB before the first code transition. “Positive full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
The deviation is measured from the middle of each particular
code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below analog common. Zero error is defined as the
deviation of the actual transition from that point. The zero error
and temperature drift specify the initial deviation and maximum
change in the zero error over temperature.
GAIN ERROR
The first code transition should occur for an analog value
1/2 LSB above nominal negative full scale. The last transition
should occur for an analog value 1 1/2 LSB below the nominal
positive full scale. Gain error is the deviation of the actual differ-
ence between first and last code transitions and the ideal differ-
ence between first and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTION
The specifications show the maximum change in the converter’s
full scale as the supplies are varied from nominal to min/max
values.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the Track-and-Hold Amplifier
(THA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time re-
quired for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
DYNAMIC SPECIFICATIONS
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is ex-
pressed as a percentage or in decibels.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb), and the third or-
der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2 fb – fa).
The IMD products are expressed as the decibel ratio of the rms
sum of the measured input signals to the rms sum of the distor-
tion terms. The two signals are of equal amplitude and the peak
value of their sums is –0.5 dB from full scale. The IMD prod-
ucts are normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
SPURIOUS FREE DYNAMIC RANGE
The difference, in dB, between the rms amplitude of the input
signal and the peak spurious signal.
ORDERING GUIDE
NOTESD = Ceramic DIP, E = Leadless Ceramic Chip Carrier.MIL-STD-883 version will be available; contact factory.
Figure 4.AD872A Typical FFT, fIN = 1 MHz, fIN Amplitude = –0.5 dB
Figure 3.AD872A Distortion vs. Input Frequency,
Full-Scale Input
105 106 107
S/(N+D) –
INPUT FREQUENCY – Hz
Figure 2.AD872A S/(N+D) Input Frequency
15dB/ DIV
15dB/ DIV
AD872A–Dynamic Characteristics–Sample Rate: 10 MSPS
Figure 6.AD872A Typical FFT, fIN = 750 kHz
Figure 7.AD872A Typical FFT, fIN = 5 MHz
15dB/ DIV
15dB/ DIV
–1 0 +1
NUMBER OF CODE HITS
THEORY OF OPERATION
The AD872A is implemented using a 4-stage pipelined multiple
flash architecture. A differential input track-and-hold amplifier
(THA) acquires the input and converts the input voltage into a
differential current. A 4-bit approximation of the input is made
by the first flash converter, and an accurate analog representa-
tion of this 4-bit guess is generated by a digital-to-analog con-
verter. This approximation is subtracted from the THA output
to produce a remainder, or residue. This residue is then sam-
pled and held by the second THA, and a 4-bit approximation is
generated and subtracted by the second stage. Once the second
THA goes into hold, the first stage goes back into track to
acquire a new input signal. The third stage provides a 3-bit ap-
proximation/subtraction operation, and produces the final resi-
due, which is passed to a final 4-bit flash converter. The 15
output bits from the 4 flash converters are accumulated in the
correction logic block, which adds the bits together using the
appropriate correction algorithm, to produce the 12-bit output
word. The digital output, together with overrange indicator, is
latched into an output buffer to drive the output pins.
The additional THA inserted in each stage of the AD872A
architecture allows pipelining of the conversion. In essence, the
converter is converting multiple inputs simultaneously, process-
ing them through the converter chain serially. This means that
while the converter is capable of capturing a new input sample
every clock cycle, it actually takes three clock cycles for the con-
version to be fully processed and appear at the output. This
“pipeline delay” is often referred to as latency, and is not a con-
cern in most applications, however there are some cases where it
may be a consideration. For example, some applications call for
the A/D converter to be placed in a high speed feedback loop,
where its input is servoed to provide a desired result at the digi-
tal output (e.g., offset calibration or zero restoration in video
applications). In these cases the three clock cycle delay through
the pipeline must be accounted for in the loop stability calcula-
tions. Also, because the converter is working on three conver-
sions simultaneously, major disruptions to the part (such as a
large glitch on the supplies or reference) may corrupt three data
samples. Finally, there will be a minimum clock rate below
which the THA droop corrupts the signal in the pipeline. In the
case of the AD872A, this minimum clock rate is 10 kHz.
The high impedance differential inputs of the AD872A allow a
variety of input configurations (see APPLYING THE AD872A),
The AD872A converts the voltage difference between the VINA
and VINB pins. For single-ended applications, one input pin
(VINA or VINB) may be grounded, but even in this case the differ-
ential input can provide a performance boost: for example, for
an input coming from a coaxial cable, VINB can be tied to the
shield ground, allowing the AD872A to reject shield noise as
common mode. The high input impedance of the device mini-
mizes external driving requirements and allows the user to exter-
nally select the appropriate termination impedance for the
application.
The AD872A clock circuitry uses both edges of the clock in its
internal timing circuitry (see spec page for exact timing require-
ments). The AD872A samples the analog input on the rising
edge of the clock input. During the clock low time (between the
While the part uses both clock edges for its timing, jitter is only
a significant issue for the rising edge of the clock (see CLOCK
INPUT section).
APPLYING THE AD872A ANALOG INPUTS
The AD872A features a high impedance differential input that
can readily operate on either single-ended or differential input
signals. Table I summarizes the nominal input voltage span for
both single-ended and differential modes, assuming a 2.5 V
reference input.
Table I.Input Voltage Span
Figure 10 shows an approximate model for the analog input cir-
cuit. As this model indicates, when the input exceeds 1.6 V
(with respect to AGND), the input device may saturate, causing
the input impedance to drop substantially and significantly re-
ducing the performance of the part. Input compliance in the
negative direction is somewhat larger, showing virtually no deg-
radation in performance for inputs as low as –1.9 V.
Figure 10.AD872A Equivalent Analog Input Circuit
Figure 11 illustrates the effect of varying the common-mode
voltage of a –0.5 dB input signal on total harmonic distortion.
AD872A
Figure 12 shows the common-mode rejection performance vs.
frequency for a 1 V p-p common-mode input. This excellent
common-mode rejection over a wide bandwidth affords the user
the opportunity to eliminate many potential sources of input
noise as common mode by using the differential input structure
of the AD872A.
INPUT FREQUENCY – Hz
CMR –
105106107108
Figure 12.Common-Mode Rejection vs. Input Frequency,
1 V p-p Input
Figures 13 and 14 illustrate typical input connections for single-
ended inputs.
Figure 13.AD872A Single-Ended Input Connection
Figure 14.AD872A Single-Ended Input Connection Using
a Shielded Cable
The cable shield is used as a ground connection for the VINB in-
put, providing the best possible rejection of the cable noise from
the input signal. Note also that the high input impedance of the
AD872A allows the user to select the termination impedance, be
it 50 ohms, or some other value. Furthermore, unlike many
flash converters, most AD872A applications will not require an
external buffer amplifier. If such an amplifier is required, we
suggest either the AD811 or AD9617.
Figure 15 illustrates how external amplifiers may be used to
convert a single-ended input into a differential signal. The resis-
Figure 15. Single-Ended to Differential Connections; U1,
U2 = AD811 or AD9617
The use of the differential input signal can help to minimize
even-order distortion from the input THA where performance
beyond –70 dB is desired.
Figure 16 shows the AD872A large signal (–0.5 dB) and small
signal (–20 dB) frequency response.
INPUT FREQUENCY – Hz
FUND
AMP –
104105106107108
Figure 16. Full Power (–0.5 dB) and Small Signal
Response (–20 dB) vs. Input Frequency
The AD872A’s wide input bandwidth facilitates rapid acquisi-
tion of transient input signals: the input THA can typically settle
to 12-bit accuracy from a full-scale input step in less than 40 ns.
Figure 17 illustrates the typical acquisition of a full-scale input
step.

Partno	Mfg	Dc	Qty	Available	Descript
AD872ASD/883B \|AD872ASD883B	AD	N/a	2	avai	Complete 12-Bit 10 MSPS Monolithic A/D Converter