AD871JD Fast Delivery |IC PHOENIX CO.,LIMITED

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AD871JD
Complete 12-Bit 5 MSPS Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
VINA
VINB
CLOCK
REF IN
REF OUT
AVDDAVSSAGNDDVDDDGND*DRVDD*DRGND
REF OUT*OUTPUT
ENABLE
OTR*MSBMSB–BIT 12
(LSB)
*ONLY AVAILABLE ON 44-TERMINAL SURFACE MOUNT PACKAGE
REV.AComplete 12-Bit 5 MSPS
Monolithic A/D Converter
FEATURES
Monolithic 12-Bit 5 MSPS A/D Converter
Low Noise: 0.17 LSB RMS Referred to Input
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.5 LSB
Signal-to-Noise and Distortion Ratio: 68 dB
Spurious-Free Dynamic Range: 73 dB
Power Dissipation: 1.03 W
Complete: On-Chip Track-and-Hold Amplifier and
Voltage Reference
Pin Compatible with the AD872
Twos Complement Binary Output Data
Out of Range Indicator
28-Lead Side Brazed Ceramic DIP or 44-Terminal
Surface Mount Package
PRODUCT DESCRIPTION
The AD871 is a monolithic 12-bit, 5 MSPS analog-to-digital
converter with an on-chip, high performance track-and-hold
amplifier and voltage reference. The AD871 uses a multistage
differential pipelined architecture with error correction logic to
provide 12-bit accuracy at 5 MSPS data rates and guarantees no
missing codes over the full operating temperature range. The
AD871 is a redesigned variation of the AD872 12-bit, 10 MSPS
ADC, optimized for lower noise in applications requiring sam-
pling rates of 5 MSPS or less. The AD871 is pin compatible
with the AD872, allowing the parts to be used interchangeably
as system requirements change.
The low-noise input track-and-hold (T/H) of the AD871 is ide-
ally suited for high-end imaging applications. In addition, the
T/H’s high input impedance and fast settling characteristics
allow the AD871 to easily interface with multiplexed systems
that switch multiple signals through a single A/D converter. The
dynamic performance of the input T/H also renders the AD871
suitable for sampling single channel inputs at frequencies up to
and beyond the Nyquist rate. The AD871 provides both refer-
ence output and reference input pins, allowing the onboard ref-
erence to serve as a system reference. An external reference can
also be chosen to suit the dc accuracy and temperature drift
requirements of the application. A single clock input is used to
control all internal conversion cycles. The digital output data is
presented in twos complement binary output format. An out-of-
range signal indicates an overflow condition, and can be used
with the most significant bit to determine low or high overflow.
The AD871 is fabricated on Analog Devices’ ABCMOS-1 pro-
cess, which uses high speed bipolar and CMOS transistors on a
single chip. High speed, precision analog circuits are now com-
bined with high density logic circuits.
The AD871 is packaged in a 28-lead ceramic DIP and a
44-terminal leadless ceramic surface mount package and is
specified for operation from 0°C to +70°C and –55°C to
+125°C.
PRODUCT HIGHLIGHTS
The AD871 offers a complete single-chip sampling 12-bit,
5 MSPS analog-to-digital conversion function in a 28-lead DIP
or 44-terminal leadless ceramic surface mount package (LCC).
Low Noise—The AD871 features 0.17 LSB referred-to-input
noise, producing essentially a “1 code wide” histogram for a
code-centered dc input.
Low Power—The AD871 at 1.03 W consumes a fraction of the
power of presently available hybrids.
On-Chip Track-and-Hold (T/H)—The low noise, high imped-
ance T/H input eliminates the need for external buffers and can
be configured for single ended or differential inputs.
Ease of Use—The AD871 is complete with T/H and voltage ref-
erence and is pin-compatible with the AD872 (12-bit, 10 MSPS
monolithic ADC).
Out of Range (OTR)—The OTR output bit indicates when the
input signal is beyond the AD871’s input range.
DC SPECIFICATIONS
INTERNAL VOLTAGE REFERENCE
POWER CONSUMPTION
NOTES
1Temperature ranges are as follows: J Grade: 0°C to +70°C, S Grade: –55°C to +125°C.
2Adjustable to zero with external potentiometers (see Zero and Gain Error Calibration section).
3+25°C to TMIN and +25°C to TMAX.
4Includes internal voltage reference error.
5Excludes internal reference drift.
6Change in Gain Error as a function of the dc supply voltage (VNOMINAL to VMIN, VNOMINAL to VMAX).
7LCC package only.
Specifications subject to change without notice.
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V, fSAMPLE = 5 MHz, unless otherwise
noted)
AD871
AC SPECIFICATIONS
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V, fSAMPLE = 5 MSPS, unless otherwise
noted)1
Specifications subject to change without notice.
NOTESfIN amplitude = –0.5 dB full scale unless otherwise indicated. All measurements referred to a 0 dB (1 V pk) input signal unless otherwise indicated.fa = 1.0 MHz, fb = 0.95 MHz with fSAMPLE = 5 MHz.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, AVSS = –5 V unless otherwise noted)
AD871
SWITCHING SPECIFICATIONS
(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V; VIL = 0.8 V,
VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
NOTESConversion rate is operational down to 10 kHz without degradation in specified performance.For clock periods of 200 ns or greater, see Clock Input section.See section on Three-State Outputs for timing diagrams and application information.
Specifications subject to change without notice.tOD
CLOCK
BIT 2–12
MSB, OTRVIN
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS1
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.LCC Package Only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD871 features proprietary ESD protection circuitry, permanent damage may
PIN FUNCTION DESCRIPTIONS
TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP, available only on
44-terminal surface mount package.
PIN CONFIGURATIONS
28-Lead Side Brazed Ceramic DIP
BIT 11
BIT 12 (LSB)
VINA
VINB
AVSS
AVDD
DVDD
DGND
AGND
OTR
CLK
REF IN
REF GND
REF OUT
AVSS
DVDD
AGND
MSBBIT 10
BIT 9
BIT 8
BIT 7
BIT 6BIT 5
BIT 4
BIT 3
BIT 2
DGND
44-Terminal LCC
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC = NO CONNECT
AVDD
AGND
DRGND
DVDD
DRVDD
CLK
OTR
MSB
AGND
DGND
DRGND
DRVDD
OEN
BIT 12 (LSB)
BIT 11NCV
INB
INA
BIT 10
BIT 9BIT 8BIT 7BIT 5BIT 4BIT 3BIT 2
BIT 1 (MSB)
BIT 6
REF INREF GNDREF OUTAV
AD871
AD871
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
DYNAMIC SPECIFICATIONS
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb), and the third or-
der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2 fb – fa).
The IMD products are expressed as the decibel ratio of the rms
sum of the measured input signals to the rms sum of the distor-
tion terms. The two signals are of equal amplitude and the peak
value of their sums is –0.5 dB from full scale. The IMD prod-
ucts are normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
SPURIOUS FREE DYNAMIC RANGE
The difference, in dB, between the rms amplitude of the input
signal and the peak spurious signal.
ORDERING GUIDE
NOTESD = Side Brazed Ceramic DIP, E = Leadless Ceramic Chip Carrier.MIL-STD-883 version will be available; contact factory.
DEFINITIONS OF SPECIFICATIONS
LINEARITY ERROR
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs
1/2 LSB before the first code transition. “Positive full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
The deviation is measured from the middle of each particular
code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value 1/2
LSB below analog common. Zero error is defined as the devia-
tion of the actual transition from that point. The zero error and
temperature drift specify the initial deviation and maximum
change in the zero error over temperature.
GAIN ERROR
The first code transition should occur for an analog value 1/2
LSB above nominal negative full scale. The last transition
should occur for an analog value 1 1/2 LSB below the nominal
positive full scale. Gain error is the deviation of the actual dif-
ference between first and last code transitions and the ideal dif-
ference between first and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTION
The specifications show the maximum change in the converter’s
full-scale as the supplies are varied from nominal to min/max
values.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the Track-and-Hold Amplifier
(THA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
INPUT FREQUENCY – Hz
10k100k10M1M
S/ (N+D) – dB
Figure 2. AD871 S/(N+D) vs. Input Frequency
Figure 3. AD871 Distortion vs. Input Frequency,
Full-Scale Input
Figure 4. AD871 Typical FFT, fIN = 1 MHz, fIN Amplitude = –0.5 dB
15dB/ DIV
AD871–Dynamic Characteristics–Sample Rate: 5MSPS
Figure 7. AD871 Typical FFT, fIN = 2 MHz
100 x p (
CODE X + 1)–1 1
1500000
1000000
500000
0
NUMBER OF CODE HITS
DEVIATION FROM CORRECT CODE (LSB)

Partno	Mfg	Dc	Qty	Available	Descript
AD871JD	AD	N/a	2	avai	Complete 12-Bit 5 MSPS Monolithic A/D Converter