AD8600AP ,16-Channel, 8-Bit Multiplying DACSpecifications subject to change without notice.–2– REV. 0AD8600(@ V = V = V = +5 V ± 5%, V = –5 V ..
AD8601ART ,Precision CMOS Single Supply Rail-to-Rail Input/Output Wideband Operational AmplifiersCHARACTERISTICSOffset Voltage V 0 V ≤ V ≤ 1.3 V 80 500 6,000 µ VOS CM–40°C ≤ T ≤ +85°C 700 7,000 µ ..
AD8601ART-REEL ,DigiTrim™ Single Rail-to-Rail Input and Output Amplifier with Very Low Offset Voltage and Wide BandwidthsCHARACTERISTICSOffset Voltage (AD8601/AD8602) V 0 V ≤ V ≤ 1.3 V 80 500 1,100 6,000 µVOS CM–40°C ≤ T ..
AD8601ART-REEL7 , Precision CMOS Single-Supply Rail-to-Rail Input/Output Wideband Operational Amplifiers
AD8601DRT-REEL7 , Precision CMOS Single-Supply Rail-to-Rail Input/Output Wideband Operational Amplifiers
AD8602A , Operational Amplifiers Selection Guide
ADS1100A3IDBVT ,Self-Calibrating, 16-Bit Analog-to-Digital ConverterABSOLUTE
ADS1100A3IDBVT ,Self-Calibrating, 16-Bit Analog-to-Digital ConverterTYPICAL CHARACTERISTICSAt T = 25°C and V = 5V, unless otherwise noted.A DD2SUPPLY CURRENT vs TEMPER ..
ADS1100A4IDBVT ,Self-Calibrating, 16-Bit Analog-to-Digital ConverterFEATURESThe ADS1100 is a precision, continuously self-calibrating* COMPLETE DATA ACQUISITION SYSTEM ..
ADS1100A4IDBVT ,Self-Calibrating, 16-Bit Analog-to-Digital ConverterFEATURESThe ADS1100 is a precision, continuously self-calibrating* COMPLETE DATA ACQUISITION SYSTEM ..
ADS1100A4IDBVTG4 ,Self-Calibrating, 16-Bit Analog-to-Digital Converter 6-SOT-23 -40 to 85Maximum Ratings” maymay be more susceptible to damage because very smallcause permanent damage to t ..
ADS1100A5IDBVT ,Self-Calibrating, 16-Bit Analog-to-Digital Converter.PIN CONFIGURATIONTop View SOT23V VIN– DD SDA65 4AD012 3V GND SCLIN+2NOTE: Marking text direction i ..
AD8600AP
16-Channel, 8-Bit Multiplying DAC
FUNCTIONAL BLOCK DIAGRAMREV.0
16-Channel, 8-Bit
Multiplying DAC
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 μs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
GENERAL DESCRIPTIONThe AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within1 LSB in 2 μs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
*Patent pending.At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
AD8600–SPECIFICATIONS
SINGLE SUPPLYANALOG OUTPUT
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
NOTESWhen VREF = 2.500 V, 1 LSB = 9.76 mV.Single supply operation does not include the final 2LSBs near analog ground. If this performance is critical, use a negative supply (VEE) pin of at least –0.7V to
–5.25V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 710 to 8010.Guaranteed by design not subject to production test.
Specifications subject to change without notice.
VDD1 = VDD2 = VCC = +5V ± 5%, VEE = 0V, VREF = +2.500V, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
LOGIC INPUTS
AC CHARACTERISTICS
POWER SUPPLIES
NOTESWhen VREF = +3.500 V, 1 LSB = 13.67 mV.Guaranteed by design not subject to production test.Settling time test is performed using RL = 50 kΩ and CL = 35 pF.Power Dissipation is calculated using 5 V × (IDD + |ISS| + IDD1 + IDD2).
Specifications subject to change without notice.
DUAL SUPPLY(@ VDD1 = VDD2 = VCC = +5V ± 5%, VEE = –5V ± 5%, VREF = +3.500V, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
AD8600
AD8600
ELECTRICAL CHARACTERISTICS
NOTESGuaranteed by design not subject to production test.All logic input signals have maximum rise and fall times of 2ns.
Specifications subject to change without notice.Figure 2. Write Timing
(@ VDD1 = VDD2 = VCC = +5V ± 5%, VEE = –5V, VREF = +3.500V, –40°C ≤ TA ≤ +85°C,
unless otherwise noted)
PIN DESCRIPTION
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS
(TA= +25°C unless otherwise noted)
VDD1 (Digital Supply) to GND . . . . . . . . . . . . . .–0.3V, +7V
VDD2 (DAC Buffer/Driver Supply) . . . . . . . . . . . .–0.3V, +7V
VCC (Analog Supply) to GND . . . . . . . . . . . . . . .–0.3V, +7V
VEE (Analog Supply) to GND . . . . . . . . . . . . . . .+0.3V, –7V
VREF to GND . . . . . . . . . . . . . . . . . . . . . .–0.3V, VCC + 0.3V
VDD2 to VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC
Short Circuit Duration
VOUT to GND or Power Supplies1 . . . . . . . . . . . . . . .Continuous
Digital Input/Output Voltage to GND . . .–0.3V, VDD + 0.3V
Thermal Resistance–Theta Junction-to-Ambient (θJA)
PLCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47°C/W
Package Power Dissipation . . . . . . . . . . . . . . . .(TJ – TA)/θJA
Maximum Junction Temperature TJ max . . . . . . . . . . .150°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
NOTENo more than four outputs may be shorted to power or GND simultaneously.
PIN CONFIGURATION
ORDERING GUIDE
*For die specifications contact your local Analog Devices sales office.
The AD8600 contains 5782 transistors.
AD8600
TRANSFER EQUATIONS
Output Voltage Oi=D×VREF256
where i is the DAC channel number and D is the decimal value
of the DAC register data.
Table I.Truth Table
NOTES+ symbol means positive edge of control input line.– symbol means negative edge of control input line.
Decoded DAC RegisterOi=A
where A is the decimal value of the decoded address bits A3,
A2, A1, A0 (LSB).
Address, CS, R/W and data inputs should be stable prior to acti-
vation of the active low EN input. Input registers are transpar-
ent when EN is low. When EN returns high, data is latched into
the decoded input register. When the load strobe LD and EN
pins are active low, all input register data is transferred to the
DAC registers. The DAC registers are transparent while they
are enabled.
Table II.Address Decode Table
111
Figure 5.Linearity Error vs.
Digital Code
Figure 8.Output Current vs.
Voltage
Figure 11.Gain & Phase vs.
Frequency
Figure 6.Full-Scale Voltage vs.
Temperature
Figure 9.Full-Scale Settling Time
Figure 12.AC Feedthrough vs.
Frequency
AD8600
Figure 14.Supply Current vs. Temperature
Operation
The AD8600 is a 16-channel voltage output, 8-bit digital to
analog converter. The AD8600 operates from a single +5 V
supply, or for a wider output swing range, the part can operate
from dual supplies of ±5 V or ±6 V or a single supply of +7 V.
The DACs are based upon a unique R-2R ladder structure*
that removes the possibility of current injection from the refer-
ence to ground during code switching. Each of the 8-bit DACs
has an output amplifier to provide 16 low impedance outputs.
With a single external reference, 16 independent dc output lev-
els can be programmed through a parallel digital interface. The
interface includes 4 bits of address (A0–A3), 8 bits of data
(DB0–DB7), a read/write select pin (R/W), an enable clock
strobe (EN), a DAC register load strobe (LD), and a chip select
pin (CS). Additionally a reset pin (RS) is provided to asynchro-
nously reset all 16 DACs to 0 V output.
D/A Converter Section
The internal DAC is an 8-bit voltage mode devicewith an out-
put that swings from DACGND to the external reference volt-
age, VREF. The equivalent schematic of one of the DACs is
shown in Figure 16. The DAC uses an R-2R ladder to ensure
accuracy and linearity over the full temperature range of the part.
The switches shown are actually N and P-channel MOSFETs to
allow maximum flexibility and range in the choice of reference
Figure 16.Equivalent Schematic of Analog Channel
Amplifier Section
The output of the DAC ladder is buffered by a rail-to-rail out-
put amplifier. This amplifier is configured as a unity gain fol-
lower as shown in Figure 16. The input stage of the amplifier
contains a PNP differential pair to provide low offset drift and
noise. The output stage is shown in Figure 17. It employs
complementary bipolar transistors with their collectors con-
nected to the output to provide rail-to-rail operation. The NPN
transistor enters into saturation as the output approaches the
negative rail. Thus, in single supply, the output low voltage is
limited by the saturation voltage of the transistor. For the tran-
sistors used in the AD8600, this is approximately 40 mV. The
AD8600 was not designed to swing to the positive rail in con-
trast to some of ADI’s other DACs (for example, the AD8582).
The output stage of the amplifier is actually capable of swinging
to the positive rail, but the input stage limits this swing to ap-
proximately 1.0 V below VCC.
Figure 17.
During normal operation, the output stage can typically source
and sink ±1 mA of current. However, the actual short circuit
current is much higher. In fact, each DAC is capable of sourc-
ing 20 mA and sinking 8 mA during a short condition. The
absolute maximum ratings state that, at most, four DACs can
be shorted simultaneously. This restriction is due to current
densities in the metal traces. If the current density is too high,
voltage drops in the traces will cause a loss in linearity perfor-
mance for the other DACs in the package. Thus to ensure long-
