AD8582AN-AD8582AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD8582AN ,+5 Volt, Parallel Input Complete Dual 12-Bit DACGENERAL DESCRIPTION The high speed parallel data interface connects to the fastestThe AD8582 is a c ..
AD8582AN ,+5 Volt, Parallel Input Complete Dual 12-Bit DACCHARACTERISTICSParameter Symbol Condition Min Typ Max UnitsSTATIC PERFORMANCEResolution N Note 1 12 ..
AD8582AN ,+5 Volt, Parallel Input Complete Dual 12-Bit DACCHARACTERISTICSCrosstalk C >64 dBT5Voltage Output Settling Time t To ±1 LSB of Final Value 16 μsSDi ..
AD8582AR ,+5 Volt, Parallel Input Complete Dual 12-Bit DACSPECIFICATIONSChip Select Pulse Width t 30 nsCSWDAC Select Setup t 30 nsASDAC Select Hold t 0nsAHDa ..
AD8591ART ,CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifiers with ShutdownApplications for these amplifiers include audio amplification for1IN A 1IN Dportable computers, por ..
AD8591ART-REEL ,Single, CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifier with ±250 mA output Current and a Power-Saving Shutdown ...CHARACTERISTICSOutput Voltage High V I = 10 mA +4.9 +4.94 VOH L–40

AD8582AN-AD8582AR
+5 Volt, Parallel Input Complete Dual 12-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
REV.0
The high speed parallel data interface connects to the fastest
processors without wait states. The double-buffered input struc-
ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re-
spective DAC registers. An address input decodes DAC A or
DAC B when the chip select CS input is strobed. An asynchro-
nous reset input sets the output to zero scale. The MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.
The AD8582 is available in the 24-pin plastic DIP and the sur-
face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
FEATURES
Complete Dual 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, ±5 mA Drive
Very Low Power: 5 mW
APPLICATIONS
Digitally Controlled Calibration
Portable Equipment
Servo Controls
Process Control Equipment
PC Peripherals
+5 Volt, Parallel Input
Complete Dual 12-Bit DAC
GENERAL DESCRIPTION
The AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. The reference (VREF) is trimmed
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. The user needs only supply a +5
volt supply.
The AD8582 is coded natural binary. The op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving ±5 mA. Operation down to
4.3 V is possible with output load currents less than 1 mA.
OUTPUT LOAD CURRENT – mA
MIN – Volts
4.8
Figure 1.Minimum Supply Voltage vs. Load
Figure 2.Linearity Error vs. Digital Code and Temperature
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VDD = +5.0 V ± 5%, RL = No Load, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
NOTES1 LSB = 1 mV for 0 V to +4.095 V output range.Includes internal voltage reference error.These parameters are guaranteed by design and not subject to production testing.Very little sink current is available at the VREF pin. Use external buffer if setting up a virtual ground.Settling time is not guaranteed for the first six codes 0 through 5.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND & AGND . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . .50 mA
Package Power Dissipation . . . . . . . . . . . . . . .(TJ max–TA)/θJA
Thermal Resistance, θJA
24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . .62°C/W
24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . .73°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . .150°C
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN DESCRIPTION
PIN CONFIGURATIONS
N-24
24-Pin Plastic DIP
SOL-24
24-Pin SOIC
LDA, LDB
A/B
D0–D11
RST
tAStAH
tDStDH
tLDW
tRSW tLH
VOUT
tCSW
Timing Diagram
ORDERING INFORMATION*
*For die specifications contact your local Analog Devices sales office. The
AD8582 contains 1270 transistors.
AD8582
Table I.Control Logic Truth Table
^Denotes positive edge triggered.
OPERATION
The AD8582 is a complete, ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. The parallel data interface consists of twelve
data bits, DB0–DB11, an address select pin A/B, two load
strobe pins (LDA, LDB) and an active low CS strobe. In addi-
tion an asynchronous RST pin will set all DAC register bits to
zero causing the VOUT to become zero volts, or to midscale for
trimming applications when the MSB pin is programmed to
Logic 1. This function is useful for power on reset or system
failure recovery to a known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an
output that swings from AGND potential to the 2.5 volt in-
ternal bandgap voltage. It uses a laser trimmed R-2R
ladderwhichisswitchedbyNchannelMOSFETs. The out-
putvoltageoftheDAChas a constant resistance independent
of digital input code. The DAC output (not available to the
user)isinternallyconnected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. The rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
The op amp has a 16 μs typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the Typical Per-
formances section of this data sheet.
Figure 3.Equivalent Schematic of Analog Portion
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FETs that
will pull an output load directly to GND. The output sourcing
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
Figure 4.Equivalent Analog Output Circuit
VDD
VOUT
AGND
P-CH
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full-scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. The voltage generated by the reference is
available at the VREF pin. Since VREF is not intended to drive ex-
ternal loads, it must be buffered. The equivalent emitter fol-
lower output circuit of the VREF pin is shown in Figure 3.
Bypassing the VREF pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 8
shows broadband noise performance.
POWER SUPPLY
The very low power consumption of the AD8582 is a direct re-
sult of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8582 is
strongly dependent on the actual logic-input voltage levels
present on the DB0–DB11, CS, A/B, MSB, LDA, LDB and
RST pins. Since these inputs are standard CMOS logic struc-
tures they contribute static power dissipation dependent on the
actual driving logic VOH and VOL voltage levels. The graph in
Figure 9 shows the effect on total AD8582 supply current as a
function of the actual value of input logic voltage. Conse-
quently, for optimum dissipation use of CMOS logic versus
TTL provides minimal dissipation in the static state. A VINL =
0 V on the DB0–11 pins provides the lowest standby dissipation
of 1 mA typical with a +5 V power supply.
As with any analog system, it is recommended that the AD8582
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8582 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current
capability near full scale can be tolerated, operation of the
AD8582 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 1, pro-
vides information for operation below VDD = +4.75 V.
TIMING AND CONTROL
The input registers are level triggered and acquire data from the
data bus during the time period when CS is low. The input reg-
ister selected is determined by the A/B select pin, see Table I.
for a complete description. When CS goes high, the data is
latched into the register and held until CS returns low. The
minimum time required for the data to be present on the bus
before CS returns high is called the data setup time (tDS) as seen
in Timing Diagram. The data hold time (tDH) is the amount
of time that the data has to remain on the bus after CS goes
high. The high speed timing offered by the AD8582 provides
for direct interface with no wait states in all but the fastest
microprocessors.
The data from the input registers is transferred to the DAC reg-
isters by the active low LDA and LDB pins. If these inputs are
tied together, a single logic input can perform a double buffer
update of the DAC registers, which in turn simultaneously
changes the analog output voltages to a new value. If the LDA
and LDB pins are wired low, they become transparent. In this
mode the input register data will directly control the output
voltages. Refer to the Control Logic Truth Table for a com-
plete description.
Unipolar Output Operation
This is the basic mode of operation for the AD8582. The
AD8582 has been designed to drive loads as low as 820Ω in par-
allel with 500 pF. The code table for this operation is shown in
Table II.
Table II.Unipolar Code Table
AD8582–Typical Performance Characteristics
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA101000100
OUTPUT SINK CURRENT – µA
OUTPUT PULL-DOWN VOLTAGE – mV100100k10k1k
OUTPUT VOLTAGE – Volts
LOAD RESISTANCE – Ω
Figure 6.Pull-Down Voltage vs.
Output Sink Current Capability
Figure 7.IOUT vs. VOUTFigure 5.Output Swing vs. Load241
LOGIC VOLTAGE VALUE – Volts
SUPPLY CURRENT – mA
100100100k10k1k
POWER SUPPLY REJECTION – dB
FREQUENCY – Hz
TIME = 100µs/DIV
OUTPUT NOISE VOLTAGE – 200µ
V/DIV
Figure 9.Supply Current vs. Logic
Input Voltage
Figure 10.Power Supply Rejection
vs. Frequency
Figure 8.Broadband Noise
TIME – 500ns/DIV
OUT
– Volts
TIME = 20µs/DIV
INPUT
OUTPUT
Figure 11.Midscale Transition
Performance
Figure 12.Large Signal Settling TimeFigure 13.Output Voltage Rise
Time Detail

Partno	Mfg	Dc	Qty	Available	Descript
AD8582AN		N/a	45	avai	+5 Volt, Parallel Input Complete Dual 12-Bit DAC
AD8582AN	PMI	N/a	157	avai	+5 Volt, Parallel Input Complete Dual 12-Bit DAC
AD8582AN	AD	N/a	10	avai	+5 Volt, Parallel Input Complete Dual 12-Bit DAC
AD8582AR	PIM	N/a	5	avai	+5 Volt, Parallel Input Complete Dual 12-Bit DAC