AD8522AN-AD8522AR-AD8522AR. Fast Delivery |IC PHOENIX CO.,LIMITED

AD8522AR ,+5 Volt, Serial Input, Dual 12-Bit DACCHARACTERISTICSPositive Supply Current I V = 5.5 V, V = 2.4 V or V = 0.8 V 3 5 mADD DD IH ILV = 5 V ..
AD8522AR. ,+5 Volt, Serial Input, Dual 12-Bit DACfeatures include a serial digi-mined by the input MSB.tal interface, onboard reference, and buffere ..
AD8527AR ,7 MHz Rail-to-Rail Low Voltage Operational AmplifiersCHARACTERISTICSOutput Voltage Swing High V I = 250 µ A,OH L–40°C ≤ T ≤ +125°C 4.965 VAI = 5 mA 4.70 ..
AD8527ARM-REEL ,7 MHz Rail-to-Rail Low Voltage Operational AmplifiersCHARACTERISTICSOffset Voltage AD8517ART (SOT-23-5) V 1.3 3.5 mVOS–40°C ≤ T ≤ +125°C5mVA AD8527 ..
AD8529AR ,8 MHz Rail-to-Rail Operational AmplifiersCHARACTERISTICSOutput Voltage Swing High V I = 250 m A +2.90 VOH LI = 5 mA +2.80 VLOutput Voltage S ..
AD8529ARM ,8 MHz Rail-to-Rail Operational AmplifiersFEATURES8-Lead SOICSpace-Saving SOT-23, mSOIC Packaging(R Suffix)Wide Bandwidth: 8 MHz @ 5 VLow Off ..
ADPLP01 ,GSM Baseband Processing ChipsetcharacteristicsThe BBC receives data at 270 kb/s. The on-chip lookup-tableand timing information.RO ..
ADR01AR ,Ultracompact Precision10 V/5 V/2.5 V/3.0 V Voltage ReferencesSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADR01ARZ-REEL7 , Ultracompact, Precision 10.0 V/5.0 V/2.5 V/3.0 V Voltage References
ADR01AUJ-R2 ,Ultracompact Precision10 V/5 V/2.5 V/3.0 V Voltage Referencesapplications. Part Number Output Voltage ADR01 10.0 V With an external buffer and a simple resisto ..
ADR01BKSZ-REEL7 , Ultracompact, Precision 10.0 V/5.0 V/2.5 V/3.0 V Voltage References
ADR01BR ,Ultracompact Precision10 V/5 V/2.5 V/3.0 V Voltage ReferencesCharacteristics, Table 2....... 4 Added ADR03...... Universal Changes to Ordering Guide .... 19 Add ..

AD8522AN-AD8522AR-AD8522AR.
+5 Volt, Serial Input, Dual 12-Bit DAC
REV.A
+5 Volt, Serial Input,
LDA
LDB
DGNDMSBRSAGNDB
AD8522
CONTROL
LOGIC
inputs. A serial data output allows the user to easily daisy-chain
multiple devices in conjunction with a chip select input. A reset
RS input sets the outputs to zero scale or midscale, as deter-
mined by the input MSB.
The output 4.095 V full scale is laser trimmed to maintain accu-
racy over the operating temperature range of the device, and
gives the user an easy-to-use one-millivolt-per-bit resolution. A
2.5 V reference output is also available externally for other data
acquisition circuitry, and for ratiometric applications. The out-
put buffers are capable of driving ±5 mA.
The AD8522 is available in the 14-pin plastic DIP and low pro-
file 1.5 mm SOIC-14 packages.
GENERAL DESCRIPTION
The AD8522 is a complete dual 12-bit, single-supply, voltage
output DAC in a 14-pin DIP, or SO-14 surface mount package.
Fabricated in a CBCMOS process, features include a serial digi-
tal interface, onboard reference, and buffered voltage output.
Ideal for +5 V-only systems, this monolithic device offers low
cost and ease of use, and requires no external components to
realize the full performance of the device.
The serial digital interface allows interfacing directly to numer-
ous microcontroller ports, with a simple high speed, three-wire
data, clock, and load strobe format. The 16-bit serial word con-
tains the 12-bit data word and DAC select address, which is de-
coded internally or can be decoded externally using LDA, LDB
DIGITAL INPUT CODE – Decimal
LINEARITY ERROR – LSB
PACKAGE TYPES AVAILABLEa
Portable Instrumentation
Cellular Base Stations Voltage Adjustment
Figure 1.Linearity Error vs. Digital Code & Temperature
AD8522–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
NOTES1 LSB = 1 mV for 0 V to +4.095 V output range.Includes internal voltage reference error.These parameters are guaranteed by design and not subject to production testing.Very little sink current is available at the VREF pin. Use external buffer if setting up a virtual ground.
(@ VDD = +5.0 V 6 10%, RL = No Load, –408C ≤ TA ≤ +858C, both DACs tested, unless
otherwise noted)
SERIAL INPUT REGISTER DATA FORMAT
LastFirst
Table I.Truth Table
NOTESIn software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high.External Pins LDA and LDB should always be high when shifting Data into the shift register.↓ symbol denotes negative transition.
1.6 VOLTSDO
CLK
SDI
tCSH
tCL
SDI
CLK
tLDW
tCLRW
±1 LSB
VOUT
SDO
Figure 2. Timing Diagram
AD8522
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND & AGND . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
Logic Inputs and Output to DGND . . . . .–0.3 V, VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
IOUT Short Circuit to GND or VDD . . . . . . . . . . . . . . . .50 mA
Package Power Dissipation . . . . . . . . . . . . . . .(TJ max–TA)/θJA
Thermal Resistance, θJA
14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . .83°C/W
14-Lead SOIC Package (SO-14) . . . . . . . . . . . . . .120°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . .150°C
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
The AD8522 contains 1482 transistors.
PIN CONFIGURATION
14-Pin Plastic DIP 14-Lead SO-14
VOUTA
AGND
VOUTB
VREF
CLK
SDI
SDO
LDA
LDB
DGND
VDD
MSB1
Table II.Truth Tables
WARNING!
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
PIN DESCRIPTION
OPERATION
The AD8522 is a complete ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. The serial data interface consists of a serial
data input (SDI), clock (CLK), and two load strobe pins (LDA,
LDB) with an active low CS strobe. In addition, an asynchro-
nous RS pin will set all DAC register bits to zero causing the
VOUT to become zero volts, or to midscale for trimming applica-
tions when the MSB pin is programmed to Logic 1. This func-
tion is useful for power on reset or system failure recovery to a
known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an out-
put that swings from AGND potential to the 2.5 V internal
bandgap voltage. It uses a laser-trimmed R-2R ladder which is
switched by N channel MOSFETs. The output voltage of the
DAC has a constant resistance independent of digital input
code. The DAC output is internally connected to the rail-to-rail
output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage that provides low offset volt-
age and low noise, as well as the ability to amplify the zero-scale
DAC output voltages. The rail-to-rail amplifier is configured in
a gain of 1.638 (= 4.095 V/2.5 V) in order to set the 4.095 V
full-scale output (1 mV/LSB). See Figure 4 for an equivalent
circuit schematic of the analog section.
SPDT
N CH FET
SWITCHES2R
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
VOUT
BANDGAP
REFERENCE
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
AV = 4.096/2.5
= 1.638V/V
Figure 4.Equivalent AD8522 Schematic of Analog Portion
The op amp has a 16 μs typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the “Typical Per-
formance Characteristics” section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 5 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FETs that
VDD
VOUT
AGND
Figure 5.Equivalent Analog Output Circuit
Figures 6 and 7 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full scale as a function of load. In addition to resis-
tive load driving capability the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. The voltage generated by the reference is
available at the VREF pin. Since VREF is not intended to drive
heavy external loads, it must be buffered. The equivalent emit-
ter follower output circuit of the VREF pin is shown in Figure 4.
Bypassing the VREF pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 10
shows broad band noise performance.
POWER SUPPLY
The very low power consumption of the AD8522 is a direct
result of a circuit design optimizing use of a CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power consumption sensitive applications it is important to
note that the internal power consumption of the AD8522 is
strongly dependent on the actual input voltage levels present on
the SDI, CLK, CS, MSB, LDA, LDB and RS pins. Since these in-
puts are standard CMOS logic structures, they contribute static
power dissipation dependent on the actual driving logic VOH and
VOL voltage levels. Consequently for optimum dissipation use of
CMOS logic versus TTL provides minimal dissipation in the static
state. A VINL = 0 V on the logic input pins provides the lowest
standby dissipation of 1 mA with a +5 V power supply.
As with any analog system, it is recommended that the AD8522
power supply be bypassed on the same PC card that contains
the chip. Figure 12 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8522 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
AD8522
input register and transferring the 12 bits of data into the de-
coded address determined by the address bits A and B in the se-
rial input register.
Unipolar Output Operation
This is the basic mode of operation for the AD8522. The
AD8522 has been designed to drive loads as low as 820 Ω in
parallel with 500 pF. The code table for this operation is shown
in Table III.
Table III. Unipolar Code Table
OUTPUT VOLTAGE – Volts
Figure 6.
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA
100µs/DIV1000100
Typical Performance Characteristics
is possible down to +4.3 V. The minimum operating supply
voltage versus load current plot, in Figure 7, provides informa-
tion for operation below VDD = +4.5 V.
TIMING AND CONTROL
The AD8522 has a 16-bit serial input register that accepts
clocked in data when the CS pin is active low. The DAC regis-
ters are updated by the Load Enable (LDA and LDB) pins.
The AD8522 offers two modes of data loading. The first mode,
hardware-load, directs the data currently clocked into the serial
shift register into either the DAC A or the DAC B register or
both depending on the external active low strobing of the LDA
or LDB pin. Serial data register bit Sf/Hd must be low for this
mode to be in effect.
The second mode of operation is software-load which is de-
signed to minimize the number of control lines connected to
the AD8522. In this mode of operation the LDA and LDB pins
act as one control input taking the present contents of the serial

Partno	Mfg	Dc	Qty	Available	Descript
AD8522AN	AD	N/a	4	avai	+5 Volt, Serial Input, Dual 12-Bit DAC
AD8522AR	AD	N/a	1204	avai	+5 Volt, Serial Input, Dual 12-Bit DAC
AD8522AR. \|AD8522AR	AD	N/a	70	avai	+5 Volt, Serial Input, Dual 12-Bit DAC