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AD8402ARU10-REEL-AD8402ARU50-AD8403ARU100-REEL-AD8403ARU10-REEL-AD8403ARU50-AD8403ARU50-REEL
0.3-8V; 1/2/4-channel digital potentiometers. For mechanical potentiometer replacement, programmable filters, delays, time constants, volume control, panning, line impendance matching, power supply adjustment
REV.C
1-/2-/4-Channel
Digital Potentiometers
FUNCTIONAL BLOCK DIAGRAM
FEATURES
256-Position
Replaces 1, 2, or 4 Potentiometers
1 k�, 10 k�, 50 k�, 100 k�
Power Shutdown—Less than 5 �A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
2.7 V to 5.5 V Single-Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTIONThe AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR) device.
These devices perform the same electronic adjustment function as
a potentiometer or variable resistor. The AD8400 contains a single
variable resistor in the compact SO-8 package. The AD8402 contains
two independent variable resistors in space-saving SO-14 surface-
mount packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each part
contains a fixed resistor with a wiper contact that taps the fixed
resistor value at a point determined by a digital code loaded into the
controlling serial input register. The resistance between the wiper and
either endpoint of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. Each variable resistor
offers a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The fixed
A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal temperature
coefficient of 500 ppm/°C. A unique switching circuit minimizes the
high glitch inherent in traditional switched resistor designs avoiding
any make-before-break or break-before-make operation.
Each VR has its own VR latch that holds its programmed resistance
value. These VR latches are updated from an SPI compatible serial-
to-parallel shift register that is loaded from a standard 3-wire
serial-input digital interface. Ten data bits make up the data word
clocked into the serial input register. The data word is decoded where
the first two bits determine the address of the VR latch to be loaded,
the last eight bits are data. A serial data output pin at the opposite end
of the serial register allows simple daisy-chaining in multiple VR
applications without additional external decoding logic.
The reset (RS) pin forces the wiper to the midscale position by
loading 80H into the VR latch. The SHDN pin forces the resistor
to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When SHDN is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made that will produce
new wiper positions when the device is taken out of shutdown.
The AD8400 is available in both the SO-8 surface-mount and the
8-lead plastic DIP package.
The AD8402 is available in both surface mount (SO-14) and
14-lead plastic DIP packages, while the AD8403 is available in a
narrow body 24-lead plastic DIP and a 24-lead surface-mount
package. The AD8402/AD8403 are also offered in the 1.1mm thin
TSSOP-14/TSSOP-24 packages for PCMCIA applications. All
parts are guaranteed to operate over the extended industrial tem-
perature range of –40°C to +125°C.
AD8400/AD8402/AD8403–SPECIFICATIONS
(VDD = 3 V � 10% or 5 V � 10%, VA = VDD, VB = 0 V,
–40�C ≤ TA ≤ +125�C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS–10 k� VERSIONDIGITAL INPUTS AND OUTPUTS
DYNAMIC CHARACTERISTICS
NOTESTypicals represent average readings at 25°C and VDD = 5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiperpositions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC29 test circuit.IW = 50 µA for VDD = 3 V and IW = 400 µA for VDD = 5 V for the 10 kΩ versions.VAB = VDD, Wiper (VW) = No Connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC28 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remainingresistor terminals are left open circuit.Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC20 for a plot of IDD versus logic voltage.PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.All Dynamic Characteristics use VDD = 5 V.Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
AD8400/AD8402/AD8403
SPECIFICATIONS(VDD = 3 V � 10% or 5 V � 10%, VA = VDD, VB = 0 V, –40�C ≤ TA ≤ +125�C unless otherwise noted.)NOTESTypicals represent average readings at 25°C and VDD = 5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiperpositions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC29 test circuit.IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.VAB = VDD, Wiper (VW) = No Connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC28 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remainingresistor terminals are left open circuit.Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
ELECTRICAL CHARACTERISTICS–50 k� and100 k� VERSIONS
AD8400/AD8402/AD8403–SPECIFICATIONS
(VDD = 3 V � 10% or 5 V � 10%, VA = VDD, VB = 0 V,
–40�C ≤ TA ≤ +125�C unless otherwise noted.)NOTESTypicals represent average readings at 25°C and VDD = 5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiperpositions. R-DNL measures the relative step change from ideal between successive tap positions. See TPC29 test circuit.IW = 500 µA for VDD = 3 V and IW = 2.5 mA for VDD = 5 V for 1 kΩ version.VAB = VDD, Wiper (VW) = No Connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC28 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC20 for a plot of IDD versus logic voltage.PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.All Dynamic Characteristics use VDD = 5 V.Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS–1 k� VERSION
AD8400/AD8402/AD8403
SPECIFICATIONS(VDD = 3 V � 10% or 5 V � 10%, VA = VDD, VB = 0 V, –40�C ≤ TA ≤ +125�C unless otherwise noted.)Figure 2a.Timing Diagram
Figure 2b.Detail Timing Diagram
Figure 2c.Reset Timing Diagram
ELECTRICAL CHARACTERISTICS–ALL VERSIONSNOTESTypicals represent average readings at 25°C and VDD = 5 V.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of 1 V/µs should be maintained.
4Propagation Delay depends on value of VDD, RL, and CL—see Applications section.
Specifications subject to change without notice.
AD8400/AD8402/AD8403
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Resistance (θJA)
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . . 180°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table I.Serial Data Word Format
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8400/AD8402/AD8403 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
NOTES
*N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO
The AD8400, AD8402, and AD8403 contain 720 transistors.
ORDERING GUIDE
AD8400/AD8402/AD8403
AD8400 PIN FUNCTION DESCRIPTIONS
AD8402 PIN FUNCTION DESCRIPTIONS
AD8403 PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
CODE – Decimal0322566496128160192224
RESISTANCE TPC1.Wiper to End Terminal
Resistance vs. Code
TPC4.10kΩ Wiper-Contact-
Resistance Histogram
WIPER RESISTANCE – �
FREQUENCY40.042.565.045.047.550.052.555.057.560.062.5TPC 7. 100kΩ Wiper-Contact-
Resistance Histogram
TPC2.Resistance Linearity vs.
Conduction Current
TPC5. Potentiometer Divider
Nonlinearity Error vs. Code
TPC 8.Nominal Resistance vs.
Temperature
TPC3.Resistance Step Position
Nonlinearity Error vs. Code
TPC6.50k� Wiper-Contact-
Resistance Histogram
TPC 9.DVWB/DT Potentiometer
Mode Tempco
AD8400/AD8402/AD8403TPC 12. 10 kΩ Gain vs. Frequency
TPC15.50kΩ Gain vs. Frequency
vs. Code
TPC18.100kΩ Gain vs. Frequency
vs. Code
TPC 10.∆RWB/∆T Rheostat Mode
Tempco
TPC13. Long-Term Drift
Accelerated by Burn-In
TPC16.Total Harmonic Distortion
Plus Noise vs. Frequency
(20mV/DIV)
(5V/DIV)
TIME 500ns/DIVTPC 11.One Position Step Change at
Half-Scale (Code 7FH to 80H)
TPC14.Large Signal Settling Time
VOUT
(50mV/DIV)
TIME 200ns/DIVTPC17.Digital Feedthrough vs. Time
