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AD8401AR
8-Bit, 4-Channel Data Acquisition System
REV.0
8-Bit, 4-Channel Data
Acquisition System
FUNCTIONAL BLOCK DIAGRAM
FEATURES
2 ms ADC with T/H
4-Channel MUX
AD899 Compatible
+5 Volt Operation
On-Chip Reference
4 ms Voltage Output DAC
Fast Bus Access Time—75 ns
APPLICATIONS
Servo Controls
Digitally Controlled Calibration
Process Control Equipment
GENERAL DESCRIPTIONThe AD8401 is a complete data acquisition and control system
containing ADC, DAC, 4-channel MUX, and internal voltage
reference. Built using CBCMOS, this monolithic circuit offers
the user a complete system with very high package density and
reliability.
The converter is a successive approximation ADC with T/H,
and is capable of operating with conversion times as short as
2 μs. Analog input bandwidth is 200 kHz, and DAC output volt-
age settling time is less than 4 μs, making the AD8401 capable
of controlling servo loops with speed and precision.
The 8-bit data interface provides both read and write operation
for parallel bus interfaces to microcontrollers and DSP proces-
sors. An external 5 MHz clock sets the 2 μs conversion rate.
Slower clocks reduce the conversion time and the internal power
dissipation. The standard control lines: Reset, Busy, Interrupt,
Read and Write complete the handshaking signals for micro-
processor communication. A start trigger ST input allows pre-
cise sampling intervals in synchronous sampling applications.
The input multiplexer addressing is designed for direct interface
to the AD899 hard-disk drive, read-channel device with no extra
hardware or special software. Analog input range levels are like-
wise compatible with the AD899.
The AD8401 is designed to operate from a single +5 volt sup-
ply, which will give an ADC input range of 0 V to 3.0 V, and
DAC output range of 0 V to 2.5 V.
The AD8401 is offered in the SOIC-28 surface mount package,
and is guaranteed to operate over the extended industrial tem-
perature range of –40°C to +85°C.
Specifications subject to change without notice.
AD8401–SPECIFICATIONS
ADC ELECTRICAL CHARACTERISTICS
Table I.Multiplexer Address Input Decode
(@ VDD = +5.0 V 6 5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; –408C ≤ TA ≤ +858C,
unless otherwise noted)
DAC ELECTRICAL CHARACTERISTICSDYNAMIC PERFORMANCE
ANALOG OUTPUT
LOGIC INPUTS (Applies to DB0–DB7, CS, WR, RD, RS)
AC CHARACTERISTICS
POWER REQUIREMENTS
Specifications subject to change without notice.
(@ VDD = +5.0 V 6 5%, AGDAC = AGADC = 0.0 V; RL = 2 kV, CL = 100 pF
to AGDAC; –408C ≤ TA ≤ +858C, unless otherwise noted)
AD8401
AD8401
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000
accumulate on the human body and test equipment and can discharge without detection.
TIMING ELECTRICAL SPECIFICATIONS
(@ VDD = +5.0 V 6 5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; –408C ≤ TA ≤ +858C,
unless otherwise noted)NOTESAll input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.t14 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.t15 is determined by t13.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . .+8 V
Input Voltages . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . .Indefinite
Package Power Dissipation . . . . . . . . . . . . . .(TJ max–TA)/θJA
Thermal Resistance θJA
28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . .53°C/W
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Junction Temperature Range (TJ max) . . . .–65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
*The AD8401 contains 1257 transistors.
Figure 1.Load Circuits for Data Access Time Testa. High Z to VOHb. High Z to VOL
Figure 2.
PIN DESCRIPTIONS
PIN CONFIGURATION
DICE CHARACTERISTICS
AD8401
OPERATIONThe AD8401 is a complete data acquisition and control system.
It contains the DAC, a four channel input multiplexer, a track/
hold, an ADC, as well as an internal bandgap reference. It inter-
faces to the microcontroller via an 8-bit digital I/O port.
D/A CONVERTER SECTIONThe DAC is an 8-bit voltage mode DAC with an output that
swings from AGDAC to the 1.25 volt bandgap voltage. It uses an
R-2R ladder fed by PNP current sources which allow the output
to swing to ground so that the DAC operates in a unipolar mode.
AMPLIFIER SECTIONThe DAC’s output is buffered by an internal high speed op
amp. The op amps output range is set at 0 V to 2.5 V. The op
amp has a 500 ns typical settling time to 0.2% for positive
slewing signals. There are differences in settling time for nega-
tive slewing signals. Signals going to zero volts will settle slightly
slower to ground than is seen in the positive direction.
Figure 3.Equivalent Amplifier Output Stage
Current sinking capability is also limited near zero volts in single
supply operation. Figure 3 provides an equivalent amplifier out-
put stage schematic.
INTERNAL REFERENCEAn on-chip bandgap is provided as a voltage reference to both
the DAC and the ADC. This reference is internal to the
AD8401 and is not accessible to the user. It is laser trimmed for
both absolute accuracy and temperature coefficients. The refer-
ence is internally buffered by a separate control amplifier for both
the DAC and ADC to improve isolation between the converters.
DIGITAL I/OThe 8-bit parallel data I/O port on the AD8401 provides access
to both the DAC and the ADC. This port is TTL/CMOS com-
patible with three-state outputs that are ESD protected.
The data format is binary. This data coding applies to both the
DAC and the ADC. See the applications information section.
ADC SECTIONA fast successive approximation ADC is used to attain a conver-
sion time of 2 microseconds. Start of conversion is initiated by
CS and RD. Following a Start command the BUSY signal will
become active and another Start command should not be given
until the conversion is complete.
The RESET (RS) input does not affect A/D conversion, but the
INT (Interrupt or conversion complete) which normally goes
Figure 4 shows the wave forms for a conversion cycle. The track
and hold begins holding the input voltage VIN approximately
50 ns after the falling edge of the Start command. The MSB de-
cision is made approximately 50 ns after the second falling edge
of the CLK. If tX is greater than 50 ns, then the falling edge of
the CLK will be seen as the first falling clock edge. If tX is less
than 50 ns, the first MSB conversion will not occur until one
clock cycle later. The following bits will each be converted in a
similar manner 50 ns after each CLK edge until all eight bits
have been converted. After the end of conversion the contents of
the ADC SAR register are transferred to the output data latch,
the track and hold is returned to the track mode, INT goes low
and the SAR is reset.
Figure 4.Operating Waveforms Using the External Clock
ANALOG INPUTThe analog inputs of the AD8401 are fed into resistor voltage
divider networks with a typical value of 8.5 kΩ. The amplifiers
driving these inputs must have an output resistance low enough
to drive these nodes without losing accuracy. Taps from the
voltage dividers are connected to the track and hold amplifier by
the multiplexer switches.
Figure 5.Equivalent Analog Input Circuit
TRACK-AND-HOLD AMPLIFIERFollowing the resistive divider at the input of the AD8401 is a
track-and-hold amplifier that captures input signals accurately
up to the 200 kHz Nyquist frequency of the ADC. To attain this
performance the T/H amplifier must have a much greater band-
width than the signal of interest. Because of this the user must
be careful to band limit the input signal to avoid aliasing high
frequency components and noise into the passband.
The track-and-hold amplifier is internally controlled by the Start
command and is not directly available to the user. After the
Start command signal the track-and-hold is placed into the hold
mode; it returns to the track mode after the conversion is
