AD8400AR10 ,1-/2-/4-Channel Digital PotentiometersCHARACTERISTICSBandwidth –3 dB BW_50K R = 50 kΩ 125 kHzBW_100K R = 100 kΩ 71 kHzTotal Harmonic Dist ..
AD8400AR-10 ,1-/2-/4-Channel Digital PotentiometersCHARACTERISTICSBandwidth –3 dB BW_10K R = 10 kΩ 600 kHzTotal Harmonic Distortion THD V = 1 V rms + ..
AD8400AR100 ,1-/2-/4-Channel Digital PotentiometersSpecifications Apply to All VRs2Resistor Differential NL R-DNL R , V = NC –1 ±1/4 +1 LSBWB A2Resist ..
AD8400AR50 ,1-/2-/4-Channel Digital PotentiometersSpecifications Apply to All VRsResolution N 8 Bits4Integral Nonlinearity INL –4 ±1 +4 LSB4Different ..
AD8400ARZ10 , 1-/2-/4-Channel Digital Potentiometers
AD8401AR ,8-Bit, 4-Channel Data Acquisition SystemGENERAL DESCRIPTION The input multiplexer addressing is designed for direct interfaceThe AD8401 is ..
ADP3338AKC-3.0-RL7 ,High Accuracy Ultralow Quiscent Current, 1A, anyCAP® Dropout RegulatorSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADP3338AKC-3.3 ,0.3-8.5V; high accuracy ultralow 1A anyCAP low dropout regulator. For notebook, palmtop computers, SCSI terminators, battery-powered systemsGENERAL DESCRIPTIONADP3338The ADP3338 is a member of the ADP33xx family of precisionV IN OUT VIN OU ..
ADP3338AKC-3.3 ,0.3-8.5V; high accuracy ultralow 1A anyCAP low dropout regulator. For notebook, palmtop computers, SCSI terminators, battery-powered systems®High-Accuracy Ultralow I , 1 A, anyCAPQaLow Dropout RegulatorADP3338FUNCTIONAL BLOCK DIAGRAM
ADP3338AKC-5 ,High-Accuracy Ultralow IQ, 1 A, anyCAP Low Dropout RegulatorSpecifications subject to change without notice.–2– REV. 0ADP3338ABSOLUTE MAXIMUM RATINGS*PIN FUNCT ..
ADP3338AKC-5-REEL ,High Accuracy Ultralow Quiscent Current, 1A, anyCAP® Dropout Regulatorapplications. The ADP3338 achieves exceptional accuracy of ±0.8% at room temperature and ±1.4% ove ..
ADP3338AKCZ-2.5RL7 , High Accuracy, Ultralow I Low Dropout Regulator
AD8400AR1-AD8400AR10-AD8400AR-10-AD8400AR100-AD8400AR50-AD8402AN10-AD8402AN-10-AD8402AN100-AD8402AR1-AD8402AR-1-AD8402AR10-AD8402AR-10-AD8402AR100-AD8402AR50-AD8402AR-50-AD8402ARU10-AD8402ARU100-AD8403AN10-AD8403AN100-AD8403AN50-AD8403AR1-AD8403AR-1-AD84
1-/2-/4-Channel Digital Potentiometers
REV.B
1-/2-/4-Channel
Digital Potentiometers
FEATURES
256 Position
Replaces 1, 2 or 4 Potentiometers
1 kV, 10 kV, 50 kV, 100 kV
Power Shut Down—Less than 5 mA
3-Wire SPI Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single-Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR)
device. These devices perform the same electronic adjustment
function as a potentiometer or variable resistor. The AD8400
contains a single variable resistor in the compact SO-8 package.
The AD8402 contains two independent variable resistors in
space saving SO-14 surface mount package. The AD8403 con-
tains four independent variable resistors in 24-lead PDIP, SOIC
and TSSOP packages. Each part contains a fixed resistor with a
wiper contact that taps the fixed resistor value at a point deter-
mined by a digital code loaded into the controlling serial input
register. The resistance between the wiper and either endpoint
of the fixed resistor varies linearly with respect to the digital
code transferred into the VR latch. Each variable resistor offers
a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ
has a ±1% channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching cir-
cuit minimizes the high glitch inherent in traditional switched
resistor designs avoiding any make-before-break or break-before-
make operation.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPI
compatible serial-to-parallel shift register that is loaded from a
standard 3-wire serial-input digital interface. Ten data bits make
up the data word clocked into the serial input register. The data
word is decoded where the first two bits determine the address
of the VR latch to be loaded, the last eight bits are data. A serial
data output pin at the opposite end of the serial register allows
simple daisy-chaining in multiple VR applications without addi-
tional external decoding logic.
The reset (RS) pin forces the wiper to the midscale position by
loading 80H into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When SHDN is returned to logic high,
the previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made which will produce
new wiper positions when the device is taken out of shutdown.
The AD8400 is available in both the SO-8 surface mount and
the 8-lead plastic DIP package.
The AD8402 is available in both surface mount (SO-14) and
the 14-lead plastic DIP package, while the AD8403 is available
in a narrow body 24-lead plastic DIP and the 24-lead surface
mount package. The AD8402/AD8403 are also offered in the
1.1mm thin TSSOP-14/TSSOP-24 package for PCMCIA ap-
plications. All parts are guaranteed to operate over the extended
industrial temperature range of –40°C to +85°C.
10 kV VERSION
ELECTRICAL CHARACTERISTICSDC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
RESISTOR TERMINALS
NOTES FOR 10 kΩ VERSIONTypicals represent average readings at +25°C and VDD = +5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = 50 μA for VDD = +3 V and IW = 400 μA for VDD = +5 V for the 10 kΩ versions.VAB = VDD, Wiper (VW) = No Connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
AD8400/AD8402/AD8403–SPECIFICATIONS
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
50 kV & 100 kV VERSIONELECTRICAL CHARACTERISTICSDC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
RESISTOR TERMINALS
NOTES FOR 50 kΩ and 100 kΩ VERSIONSTypicals represent average readings at +25°C and VDD = +5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = VDD/R for VDD = +3 V or +5 V for the 50 kΩ and 100 kΩ versions.VAB = VDD, Wiper (VW) = No Connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
AD8400/AD8402/AD8403
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
SPECIFICATIONS
1 kV VERSION
ELECTRICAL CHARACTERISTICSNOTES FOR 1 kΩ VERSIONTypicals represent average readings at +25°C and VDD = +5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit.
IW = 500 μA for VDD = +3 V and IW = 4 mA for VDD = +5 V for 1 kΩ version.VAB = VDD, Wiper (VW) = No Connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of IDD versus logic voltage.9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
AD8400/AD8402/AD8403–SPECIFICATIONS
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
All VERSIONS
ELECTRICAL CHARACTERISTICSNOTESTypicals represent average readings at +25°C and VDD = +5 V.Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/μs should be maintained.Propagation Delay depends on value of VDD, RL and CL–see applications text.
Specifications subject to change without notice.
AD8400/AD8402/AD8403–SPECIFICATIONS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
(VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –408C ≤ TA ≤ +858C unless
otherwise noted)
DAC REGISTER LOAD
VDD
0V
SDI
CLK
VOUTFigure 1a. Timing Diagram
±1 % ERROR BAND
tPD_MINtPD_MAX
VDD
SDI
(DATA IN)
CLK
VOUT
SDO
(DATA OUT)Figure 1b.Detail Timing Diagram
Figure 1c.Reset Timing Diagram
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ max) . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance (θJA)
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD8400/AD8402/AD8403
Table I.Serial Data Word Format
PIN CONFIGURATIONS
ORDERING GUIDEAD8400AN50
AD8400AR50
AD8402AN50
AD8402AR50
AD8403AN50
AD8400AN100
AD8400AR100
AD8402AN100
AD8402AR100
AD8402ARU100
AD8403AN100
AD8403AR100
AD8400AN1
AD8400AR1
AD8402AN1
AD8402AR1
AD8403AN1
AD8403AR1
*N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO.
The AD8400, AD8402 and the AD8403 contain 720 transistors.
AD8400 PIN DESCRIPTIONS
AD8402 PIN DESCRIPTIONS*All AGNDs must be connected to DGND.
AD8403 PIN DESCRIPTIONS*All AGNDs must be connected to DGND.
CODE – Decimal322566496128160192224
RESISTANCE – kFigure 2.Wiper to End Terminal
Resistance vs. Code
DIGITAL INPUT CODE – Decimal
R-INL ERROR – LSBFigure 5.Resistance Step Position
Nonlinearity Error vs. Code
DIGITAL INPUT CODE – Decimal
INL NONLINEARITY ERROR – LSBFigure 8.Potentiometer Divider
Nonlinearity Error vs. Code
AD8400/AD8402/AD8403–Typical Performance Characteristics
IWA CURRENT – mA1456
VOLTAGE – VFigure 3.Resistance Linearity vs.
Conduction Current
WIPER RESISTANCE – Ω
FREQUENCY40.042.565.045.047.550.052.555.057.560.062.5Figure 6.10kΩ Wiper-Contact-
Resistance Histogram
WIPER RESISTANCE – Ω
FREQUENCY3537553941434547495153Figure 9.50kΩ Wiper-Contact-
Resistance Histogram
WIPER RESISTANCE – Ω
FREQUENCY40.042.565.045.047.550.052.555.057.560.062.5Figure 4.100kΩ Wiper-Contact-
Resistance Histogram
TEMPERATURE – °C
NOMINAL RESISTANCE –
–75–50125–250255075100Figure 7.Nominal Resistance vs.
Temperature
Figure 10.DVWB/DT Potentiometer
Mode Tempco
AD8400/AD8402/AD8403
FREQUENCY – Hz10k1M
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
100k1001kFigure 20.Normalized Gain Flat-
ness vs. Frequency
FREQUENCY – Hz
GAIN – dB10k1M
100kFigure 23.–3dB Bandwidths
FREQUENCY – Hz
100k2M200k1M
400k4M6M
PHASE – Degrees
10M
GAIN – dB Figure 26.1 kΩ Gain and Phase
vs. Frequency
INPUT LOGIC VOLTAGE – Volts
IDD
– SUPPLY CURRENT – mA
0.1Figure 21.Supply Current vs. Logic
Input Voltage
FREQUENCY – Hz1M10M10k100k
– SUPPLY CURRENT – µA
200Figure 24.Supply Current vs.
Clock Frequency
SHUTDOWN CURRENT – nA
TEMPERATURE – °CFigure 27.Shutdown Current vs.
Temperature
FREQUENCY – Hz
PSRR – dB1001M1k10k100kFigure 22.Power Supply Rejection
vs. Frequency
Figure 25.AD8403 Incremental
Wiper ON Resistance vs. VDD
Figure 28.Supply Current vs.
Temperature
