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AD8392ARE-AD8392ARE-REEL7-AD8392AREZ-AD8392AREZ-REEL7
Low Power, High Output Current, Dual Channel ADSL/ADSL2+ Line Driver
Low Power, High Output Current, Quad Op Amp,
Dual-Channel ADSL/ADSL2+ Line Driver
Rev. 0
FEATURES
Four current feedback, high current amplifiers
Ideal for use as ADSL/ADSL2+ dual-channel Central Office
(CO) line drivers
Low power operation
Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V)
Less than 3 mA/Amp quiescent supply current for full
power ADSL/ADSL2+ CO applications (20.4 dBm line
power, 5.5 CF)
Three active power modes plus shutdown
High output voltage and current drive
400 mA peak output drive current
44 V p-p differential output voltage
Low distortion
−72 dBc @1 MHz second harmonic
−82 dBc @ 1 MHz third harmonic
High speed: 900 V/µs differential slew rate
Additional functionality of AD8392ACP
On-chip common-mode voltage generation
APPLICATIONS
ADSL/ADSL2+ CO line drivers
XDSL line drives
High output current, low distortion amplifiers
DAC output buffer
GENERAL DESCRIPTION The AD8392 is comprised of four high output current, low
power consumption, operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver is capable of
providing enough power to deliver 20.4 dBm to a line, while
compensating for losses due to hybrid insertion and back
termination resistors. In addition, the low distortion, fast slew
rate, and high output current capability make the AD8392 ideal
for many other applications, including medical, instrumenta-
tion, DAC output drivers, and other high peak current circuits.
The AD8392 is available in two thermally enhanced packages, a
28-lead TSSOP EP (AD8392ARE) and a 5 mm × 5 mm 32-lead
LFCSP (AD8392ACP). Four bias modes are available via the use
of two digital bits (PD1, PD0).
PIN CONFIGURATIONS
NC = NO CONNECT
PD0 1, 2
PD1 1, 2
+VIN1
VOUT1
–VIN1
VEE1, 2
+VIN2
VOUT2
–VIN2
VOUT3
–VIN3
+VIN3
GND
VCC3, 4
–VIN4
+VIN4
VEE3, 4
PD0 3, 4
PD1 3, 4
GND
VCC1, 2
VOUT4Figure 1. AD8392ARE, 28-Lead TSSOP/EP
VOUT1
–VIN1
1, 2+V
VOUT2
–VIN2
VOUT3
–VIN3
GND
VCC3, 4
–VIN4
3, 4
0 3, 4
GND
VOUT4
COM
3, 4
1 3, 4
COM
1, 2
1 1, 2
0 1, 2Figure 2. AD8392ACP, 32-Lead LFCSP 5 mm × 5 mm
Additionally, the AD8392ACP provides VCOM pins for on-chip
common mode voltage generation.
The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the AD8392
to be used as the CO line drivers in ADSL and other xDSL sys-
tems, as well as other high current, single-ended or differential
amplifier applications.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Thermal Resistance......................................................................5
ESD Caution..................................................................................5
Typical Performance Characteristics.............................................6
Theory of Operation......................................................................11
Applications.....................................................................................12
Supplies, Grounding, and Layout.............................................12
Resistor Selection........................................................................12
Power Management...................................................................12
Driving Capacitive Loads..........................................................12
Thermal Considerations............................................................13
Typical ADSL/ADSL2+ Application........................................13
Multitone Power Ratio...............................................................14
Lightning and AC Power Fault.................................................15
Outline Dimensions.......................................................................16
Ordering Guide..........................................................................16
REVISION HISTORY
7/04—Revision 0: Initial Version SPECIFICATIONS VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.
Table 1. VS = ±5 V or +10 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.
Table 2. ABSOLUTE MAXIMUM RATINGS
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Maximum Power Dissipation The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load (RL) is midsupply,
the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
RMS output voltages should be considered. If RL is referenced
to VS− as in single-supply operation, the total power is VS × IOUT.
In single supply with RL to VS−, worst case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the LFCSP-32 and
TSSOP-28/EP packages on a JEDEC standard 4-layer board. θJA
values are approximations.
TEMPERATURE (°C)
XIM
POW
ISSIPA
TIONFigure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
See the Thermal Considerations section for additional thermal
design guidance.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT POWER (dBm)
MULTITONE
R RATIO (dBc
–60191704802-0-004
Figure 4. MTPR vs. Output Power (1.75 MHz Empty Bin)
ADSL/ADSL2+ Circuit (Figure 32)
VS = ±12 V, RLOAD = 100 Ω, CF = 5.45
FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
Figure 5. Harmonic Distortion vs. Frequency
Dual Differential Driver Circuit (Figure 30)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 2 V p-p
FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–90–60
Figure 6. Harmonic Distortion vs. Frequency
OUTPUT POWER (dBm)
R CONS
UMP
ION (mW)950161718192021
Figure 7. Power Consumption vs. Output Power (26 kHz to 2.2 MHz)
ADSL/ADSL2+ Circuit (Figure 32)
VS = ±12 V, RLOAD = 100 Ω, CF = 5.45
FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
Figure 8. Harmonic Distortion vs. Frequency
Dual Differential Driver Circuit (Figure 30)
VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 2 V p-p
FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–90–60
Figure 9. Harmonic Distortion vs. Frequency
FREQUENCY (MHz)
GAIN (0
Figure 10. Small Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p
–20
–15
–10
–5
FREQUENCY(MHz)GAIN (
Figure 11. Small Signal Frequency Response vs. Load
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, G = +5, VOUT = 100 mV p-p
FREQUENCY (MHz)
GAIN (0
Figure 12. Large Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p
FREQUENCY (MHz)0
Figure 13. Small Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p
FREQUENCY (MHz)
IGNAL FE
THROUGH (dB)
0.111000–10100
Figure 14. Signal Feedthrough vs. Frequency
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1)
FREQUENCY (MHz)
GAIN (0
Figure 15. Large Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p
TIME (µs)OUTPUT VOLTAGE (V)
Figure 16. Small Signal Pulse Response
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, 100 mV Step
Figure 17. Power-Up Time: PD (1, 1) to PD (0, 0)
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p
Figure 18. Input Overdrive Recovery
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +1, VIN = 27 V p-p
TIME (µs)OUTPUT VOLTAGE (V)
2.5
Figure 19. Large Signal Pulse Response
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, 4 V Step
Figure 20. Power-Down Time: PD (0, 0) to PD (1, 1)
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p
Figure 21. Output Overdrive Recovery
Quad Op Amp Circuit (Figure 29)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VIN = 6 V p-p
