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AD8382ACPZ
High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver®
High Performance 12-Bit, 6-Channel Output,
Decimating LCD DecDriver®
PRODUCT FEATURES
High accuracy, high resolution voltage outputs 12-bit input resolution
Laser trimmed outputs
Fast settling, high voltage drive 33 ns settling time to 0.25% into 200 pF load Slew rate 390 V/µs Outputs to within 1.3 V of supply
High update rates Fast, 120 Ms/s data update rate
Voltage controlled video reference (brightness) and full-scale (contrast) output levels
Flexible logic STSQ/XFR allow parallel AD8382 operation
INV bit reverses polarity of video signal
Output overload protection
Low static power dissipation: 743 mW
Includes STBY function
3.3 V logic, 9 V to 18 V analog supplies
Available in 48-lead 7 mm × 7 mm LFCSP
APPLICATIONS
LCD analog column driver
PRODUCT DESCRIPTION The AD8382 DecDriver provides a fast, 12-bit latched decimat-
ing digital input that drives six high voltage outputs.12-bit input
words are sequentially loaded into six separate, high speed,
bipolar DACs. A flexible digital input format allows several
AD8382s to be used in parallel for higher resolution displays.
STSQ synchronizes sequential input loading, XFR controls
synchronous output updating, and R/L controls the direction of
loading as either left-to-right or right-to-left. Six channels of
high voltage output drivers drive to within 1.3 V of the rail. The
output signal can be adjusted for dc reference, signal inversion,
and contrast for maximum flexibility.
The AD8382 is fabricated on Analog Devices’ XFHV, fast
bipolar 26 V process, providing fast input logic bipolar DACs
with trimmed accuracy and fast settling, high voltage, precision
drive amplifiers on the same chip. The AD8382 dissipates
743 mW nominal static power. The STBY pin reduces power to
a minimum, with fast recovery.
FUNCTIONAL BLOCK DIAGRAM
VREFHIVREFLO
STBY
BYP
R/L
E/O
CLK
STSQ
XFR
INVV1V2
DB(0:11)Figure 1. Functional Block Diagram
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Timing Characteristics.....................................................................6
Pin Configuration and Functional Descriptions..........................7
Typical Performance Characteristics.............................................8
Functional Description..................................................................13
Transfer Function.......................................................................13
Accuracy......................................................................................14
Applications.....................................................................................15
VBIAS Generation—V1, V2 Input Pin Functionality...........17
Power Supply Sequencing.........................................................18
PCB Design for Optimized Thermal Performance...............18
Layout Considerations...............................................................20
Outline Dimensions.......................................................................21
Ordering Guide..........................................................................21
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TMIN = 0°C, TMAX = 85°C, VREFHI = 9.5 V, VREFLO = V1 = V2 = 7 V, unless
otherwise noted. mV mV mV mV
V V µA µA V V V kΩ µA µA V
1 VDE = differential error voltage. VCME = common-mode error voltage. ∆V = maximum deviation between outputs.
Full-scale output voltage = VFS = 2 × (VREFHI – VREFLO). See the Accu section on page 14. racy Measured on two outputs differentially as CLK and DB(0:11) are driven and STSQ and XFR are held LOW. Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV.
4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV. Operation at 85°C ambient temperature requires a thermally optimized PCB layout (see section), minimum airflow of 200 lfm, input clock rate not
exceeding 120 MHz, black-to-white transition ≤ 4 V, and CL ≤ 200 pF.
Applications
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings1 Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may reduce
device reliability.
2 48-lead LFCSP Package:
θJA = 26°C/W (JEDEC STD, 4-layer PCB in still air) θJC = 20°C/W.
ΨJB = 11°C/W in Still Air
OVERLOAD PROTECTION The AD8382 employs a two-stage overload protection circuit
that consists of an output current limiter and a thermal
shutdown. The maximum current at any output of the AD8382
is internally limited to 100 mA average. In the event of a
momentary short circuit between a video output and a power
supply rail (VCC or AGND), the output current limit is
sufficiently low to provide temporary protection.
The thermal shutdown “debiases” the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short circuit between a video output and
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typ. with a period set by the
thermal time constant and hysteresis of the thermal trip point.
The thermal shutdown provides long-term protection by
limiting average junction temperature to a safe level.
EXPOSED PADDLE To ensure a high degree of reliability, the exposed paddle must
be electrically connected to AVCC.
To ensure optimized thermal performance, the exposed paddle
must be thermally connected to the AVCC plane as described in
the Applications section.
MAXIMUM POWER DISSIPATION The maximum power that the AD8382 can safely dissipate is
limited by its junction temperature. The maximum safe junction
temperature for plastic encapsulated devices, as determined by
the plastic’s glass transition temperature, is approximately
150°C. Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in stresses exerted on
the die by the package. Exceeding a junction temperature of
175°C for extended periods can result in device failure.
OPERATING TEMPERATURE RANGE Although the maximum safe operating junction temperature is
higher, the AD8382 is 100% tested at a junction temperature of
125°C. Consequently, the maximum guaranteed operating
junction temperature is 125°C. To ensure operation within the
specified operating temperature range, it is necessary to limit
the maximum power dissipation to: 39.0–(θ–(TPJMAX
DMAX×≈
where TJMAX = 125°C
MAXIMUM AMBIENT TEMPERATURE (°C)
POW
ISSIPA
TION
AD8382 ON A 4–LAYER JEDEC PCB WITH THERMALLY OPTIMIZED
LANDING PATTERN AS DESCRIBED IN THE APPLICATION NOTESFigure 2. Maximum Power Dissipation vs. Temperature.
Note: Quiescent power dissipation is 0.74 W when operating under the conditions specified in this data sheet.
When driving a 6-channel XGA panel with an input capacitance
of 200 pF, the AD8382 dissipates a total of 1.14 W when
displaying 1 pixel wide alternating white and black vertical lines
generated by a standard 60 Hz XGA input video.
The total power dissipation of the AD8382 is 1.67 W when
operating at the maximum specified frequency of 120 MHz,
under the conditions specified in this data sheet (Figure 2).
TIMING CHARACTERISTICS
Table 3. Timing Parameters and Conditions ns
CLK
DB(0:11)
STSQ
XFR Figure 3. Timing Requirement E/O = HIGH
CLK
DB(0:11)
STSQ
XFRFigure 4. Timing Requirement E/O = LOW
CLK
INV
XFRFigure 5. Output Timing
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
NC = NO CONNECT
AD8382
TOP VIEW
(Not to Scale)
DB0
DB1
DB2
DB3
DB4
VID0
AVCC0,1
VID1
VID2
DB5
DB6
DB7
DB8
DB9
AVCC2,3
VID3
VID4
AVCC4,5
DB10VID5
DB11AGND5
PIN 1INDICATOR
E/O
R/L
INV
DGND
CLKXFRSTSQNCNC
CCBIAS
STB
AGNDBIASAV
CCDAC
EFH
EFLO
AGND0Figure 6. 48-Lead LFCSP, 7 mm × 7 mm Package
Table 4. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
TIME (ns)
OUTPUT (
–20020406080100120140160180Figure 7. Output Settling Time (Rising Edge),
CL = 200 pF, 5 V Step, INV = LOW
TIME (ns)
OUTPUT (
–20020406080100120140160180Figure 8. Output Settling Time (Rising Edge),
CL = 200 pF, 5 V Step, INV = HIGH
TIME (ns)
OUTPUT (
0.25%/D
–150153045607590105120135Figure 9. Output Settling Time (Rising Edge) vs. CL,
TIME (ns)
OUTPUT (
–20020406080100120140160180Figure 10. Output Settling Time (Falling Edge),
CL = 200 pF, 5 V Step, INV = LOW
TIME (ns)
OUTPUT (
–20020406080100120140160180Figure 11. Output Settling Time (Falling Edge),
CL = 200 pF, 5 V Step, INV = HIGH
TIME (ns)
OUTPUT (
0.25%/D
–150153045607590105120135Figure 12. Output Settling Time (Falling Edge) vs. CL,
TIME (ns)
ITC
STEP R
ESPON
SE (Figure 13. Invert Switching Step Response (Rising Edge),
10 V Step, CL = 200 pF
TIME (ns)
ITC
STEP R
ESPON
SE (Figure 14. Data Switching Step Response (Rising Edge),
5 V Step, CL=200 pF, INV = LOW
TIME (ns)
ITC
STEP R
ESPON
SE (Figure 15. Data Switching Step Response (Rising Edge),
5 V Step, CL = 200 pF, INV = HIGH
TIME (ns)
ITC
STEP R
ESPON
SE (Figure 16. Invert Switching Step Response (Falling Edge),
10 V Step, CL = 200 pF
TIME (ns)
ITC
STEP R
ESPON
SE (Figure 17. Data Switching Step Response (Falling Edge),
5 V Step, CL = 200 pF, INV = LOW
TIME (ns)
ITC
STEP R
ESPON
SE (Figure 18. Data Switching Step Response (Falling Edge),
5 V Step, CL = 200 pF, INV = HIGH
INPUT CODE
DNL (LS
2.05121024153620482564307235844096Figure 19. Differential Nonlinearity (DNL) vs. Code, INV = LOW
INPUT CODE
INL (
SB)
2.05121024153620482564307235844096Figure 20. Integral Nonlinearity (INL) vs. Code, INV = LOW
INPUT CODE
(mV
3.5005121024153620482564307235844096Figure 21. Common-Mode Error Voltage (VCME) vs. Code
INPUT CODE
DNL (LS
2.05121024153620482564307235844096Figure 22. Differential Nonlinearity (DNL) vs. Code, INV = HIGH
INPUT CODE
INL (
SB)
2.05121024153620482564307235844096Figure 23. Integral Nonlinearity (INL) vs. Code, INV = HIGH
INPUT CODE
E (
5.005121024153620482564307235844096Figure 24. Differential Error Voltage (VDE) vs. Code
– V1 (V)IZED
VD
E, VC1.02.03.04.05.06.0Figure 25. Normalized VDE, VCME vs. (V2 – V1) at Code 2048
V2 (V) @ V1 = 7VV1 (V) @ V2 = 7V
IZED
VD
E (
–10Figure 26. Normalized VDE vs. V1 and V2 at Code 2048
TEMPERATURE (°C)
(mV
3.500Figure 27. Common-Mode Error Voltage (VCME) vs. Temperature
V1 = V2 (V)
IZED
VD
E, VC
5.06.07.08.09.010.011.0Figure 28. Normalized VDE, VCME vs. V1 = V2 at Code 2048
VREFLO (V)
IZED
VD
E, VC67891011121314Figure 29. Normalized VDE, VCME vs. VREFLO at Code 2048
TEMPERATURE (°C)
E (
0302010405060708090100Figure 30. Differential Error Voltage (VDE) vs. Temperature
TIME (ns)
VID
7.05Figure 31. All-Hostile Crosstalk at CL = 200 pF
LOAD CAPACITANCE (pF)
SLEW
E (Figure 32. Slew Rate vs. CL (Falling Edge)
FREQUENCY (Hz)
PSR
10k1k10010100k1M10MFigure 33. AVCC Power Supply Rejection vs. Frequency
TIME (ns)
VID
7.05Figure 34. Data Switching Transient (Feedthrough) at CL = 200 pF
LOAD CAPACITANCE (pF)
SLEW
E (Figure 35. Slew Rate vs. CL (Rising Edge)
