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AD8380JS
Fast, High-Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver
REV.B
Fast, High-Voltage Drive, 6-Channel Output
DecDriver™ Decimating LCD Panel Driver
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High-Voltage Drive to Within 1.3 V of Supply Rails
24 V Supply for Fast Output Voltage Drivers
High Update Rates:Fast 75 Ms/s 10-Bit Input Word Rate
Low Power Dissipation, 550 mW with Power-Down
Voltage Controlled Video Reference and Full-Scale
(Contrast) Output Levels
INV Bit Reverses Polarity of Video Signal
Nominal 3.3 V Logic and 15 V Analog Supplies
Flexible Logic
Addressable or Sequential Channel Loading
STSQ/CS Allow Parallel AD8380 Operation for XGA
and Greater Resolution
Drives Capacitive Loads
26 ns Settling Time to 1% Up to 150 pF Load
Slew Rate 270 V/�s
Available in 44-Lead MQFP
APPLICATIONS
Poly Si LCD Panel Analog Column Driver
PRODUCT DESCRIPTIONThe AD8380 provides a fast, 10-bit latched decimating digital
input that drives 6-channel high voltage drive outputs. The 10-
bit input word is sequentially muxed into six separate high speed,
bipolar DACs. Flexible digital input formats allow several
AD8380s to be used in parallel for higher resolution displays.
STSQ/CS, in conjunction with 3-bit addressable channel-loading
pins, allows loading of the digital words either sequentially or
randomly, and R/L control sets loading as either left to right, or
vice versa. 6-channel high voltage output drivers drive to within
1.3 V of the rails to rated settling time. The output signal can be
adjusted for dc signal reference, signal inversion or contrast for
maximum flexibility.
The AD8380 is fabricated on ADI’s XFCB26 fast bipolar 26 V
process, providing fast input logic, trimmed accuracy bipolar
DACs and fast settling, high voltage precision drive amplifiers
on the same chip.
The AD8380 dissipates nominally 0.55 W of static power. STBY
pin reduces power to a minimum, with fast recovery.
The AD8380 is offered in a 44-lead 10 × 10 × 2.0 mm MQFP
package and operates over the commercial temperature range of
0°C to 85°C.
DecDriver is a trademark of Analog Devices, Inc.
AD8380–SPECIFICATIONS
(@ 25�C, AVCC = 15 V, DVCC = 3.3 V, TMIN = 0�C, TMAX = 85�C, unless
otherwise noted)NOTESFor definitions of VDE and VCME, see the Transfer Function section. Scale factor error is expressed as percentage of VFS.See Figure 1 for valid ranges of VMID.VREFHI Input Current = (VREFHI – VREFLO)/(VREFHI Input Resistance) = 2.5 V/3.3 kΩ.
PIN FUNCTION DESCRIPTIONS
CHANNEL SELECTION FUNCTIONALITYThere are two channel selection modes, addressed channel
loading, (in which the user directly controls which DAC is
loaded), and internally sequenced loading (in which the user
controls the direction and clock phase in which the loading
proceeds).
ADDRESSED CHANNEL LOADING:When channel address (A0, A1, A2) = 000 through 101, the
video data is loaded into Channels 0 through 5. (STSQ/CS
functions as “Chip Selection” this case.)
INTERNALLY SEQUENCED LOADING:When channel address = 111 the video data is loaded in a
sequence determined internally. The sequencing is initiated by
a pulse applied to STSQ/CS input. The count proceeds from
0 to 5 if R/L is LOW or from 5 to 0 if R/L is HIGH.
DAC TRANSFER FUNCTIONVOUT = VMID + VFS × (1 – N/1023); if INV is HIGH,
VOUT = VMID – VFS × (1 – N/1023); if INV is LOW
where VFS = 2 × (VREFHI – VREFLO)
MAXIMUM OUTPUT VOLTAGEThe maximum output signal swing is constrained by the output
voltage compliance of the DACs and the output dynamic range
of the output amplifiers. The minimum voltage allowed at the
outputs of the DACs is about 6 V. This constrains the minimum
value of VMID to be 6 V. The output amplifiers will swing and
settle cleanly, as described on the specification page, for output
voltages within 1.5 V from each supply voltage rail.
For a given value of VMID, the voltage required to saturate the
video output voltages defines the maximum usable full-scale
voltage. For example, if VMID is less than AVCC/2, the maxi-
mum value of VFS is (VMID – 1.5 V). If VMID is greater than
AVCC/2, the maximum useful VFS is (AVCC – 1.5 – VMID).
Figure 1 graphically describes these limiting factors.
AD8380
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ABSOLUTE MAXIMUM RATINGS1SupplyVoltage AVCC–AVEE . . . . . . . . . . . . . . . . . . . . . 26V
InternalPowerDissipation2
Quad FlatPackage (S) . . . . . . . . . . . . . . . . . . . . . . . 1.7W
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Associated Text
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . 0°C to 85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . .300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
44-Lead MQFP Package: θJA = 73°C/W (Still Air), where PD = (TJ – TA)/θJA.
θJC = 22°C/W.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8380 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175°C for an extended period can result in
device failure.
Output Short Circuit LimitThe AD8380’s internal short circuit limitation is not sufficient to
protect the device in the event of a direct short circuit between a
video output and a power supply voltage rail (VCC or VEE). Tem-
porary short circuits can reduce an output’s ability to source or
sink current and, therefore, impact the device’s ability to drive a
load. Short circuits of extended duration can cause metal lines to
fuse open, rendering the device nonfunctional.
To prevent these problems, it is recommended that a series
resistor of 25 Ω or greater be placed as close as possible to the
AD8380’s video outputs. This will serve to substantially reduce
the magnitude of the fault currents and protect the outputs from
damage caused by intermittent short circuits. This may not be
enough to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power derat-
ing curve in Figure 2 below.
Figure 2.Maximum Power Dissipation vs. Temperature
PIN CONFIGURATION
NC = NO CONNECT
AVCC0,1
DB8
(MSB) DB9
CLK
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
INV
DVEE
DVCC
AVCC BIAS
STBY
BYP
AVEE BIAS
VMID
AVEE5
VID0
VID1
AVEE1,2
VID2
AVCC2,3
VID3
AVEE3,4
VID4
AVCC4,5
VID5
XFRSTSQ/CSA0A1A2AVCCDACAVEEDACVREFHIVREFLOAVEE0
ORDERING GUIDE
20ns/DIV
1.25V/DIV
VMID + VFS
VMID – VFSTPC 1.Invert Switching 10 V Step Response (Rise) at CL
TPC 2.Invert Switching 10 V Step Response (Fall) at CL
TPC 3.Data Switching Full-Scale Step Response (Rise) at
CL, INV = L
TPC 4.Data Switching Full-Scale Step Response (Fall) at
CL, INV = L
TPC 5.Data Switching Full-Scale Step Response (Rise) at
CL, INV = H
TPC 6.Data Switching Full-Scale Step Response (Fall) at
CL, INV = H
AD8380
10ns/DIV
VMID+ VFS
OUTPUT VOLTAGE ERROR
1%/DIVTPC 7.Output Settling Time Response to 1% of Full
Scale (Rising Edge) at CL
TPC 8.Output Settling Time Response to 1% of Full
Scale (Falling Edge) at CL
TPC 9.Output Settling Time Response to 0.25% of Full
Scale (Rising Edge) at CL
TPC 10.Output Settling Time Response to 0.25% of Full
Scale (Falling Edge) at CL
TEMPERATURE – �C
VDE
mV
7.5203040507080TPC 11.Differential Error Voltage (VDE) vs. Temperature
TEMPERATURE – �C
VCME
mV
–2.5TPC 12.Common-Mode Error Voltage (VCME) vs.
Temperature
CODE
DNL
LSB
0.5TPC 13.Differential Nonlinearity (DNL) vs. Code, INV = H
CODE
DNL
LSB
0.5TPC 14.Differential Nonlinearity (DNL) vs. Code, INV = L
CODE
VDE
mV
7.5TPC 15.Differential Error Voltage (VDE) vs. Code
CODE
INL
LSB
0.5TPC 16.Integral Nonlinearity (INL) vs. Code, INV = H
CODE8967686405123842561281024–0.5
INL
LSB
0.5TPC 17.Integral Nonlinearity (INL) vs. Code, INV = L
CODE
VCME
mV
3.5TPC 18.Common-Mode Error Voltage (VCME) vs. Code
AD8380TPC 19.Clock Switching Transient (Feedthrough) at CL
TPC 20.Data Switching Transient (Feedthrough) at CL
TPC 21.All-Hostile Crosstalk at CL
FREQUENCY – Hz
10k5M100k
PSRR
dBTPC 22.AVCC Power Supply Rejection vs. Frequency
