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ADP3333ARM-3.15 ,0.3-16V; high accuracy ultralow Iq, 300mA, anyCAP low dropout regulator. For cellular phones, PCMCIA cards, personal digital assistants (PDAs), DSP/ASIC suppliesSpecifications subject to change without notice.–2– REV. 0ADP3333PIN FUNCTION DESCRIPTIONSABSOLUTE ..
ADP3333ARM-3.15-RL ,High Accuracy Ultralow IQ, 300 mA, anyCAP® Low Dropout RegulatorFEATURES FUNCTIONAL BLOCK DIAGRAMHigh Accuracy over Line and Load: 0.8% @ 25C,1.8% Over Temperat ..
ADP3333ARM-3.3 ,0.3-16V; high accuracy ultralow Iq, 300mA, anyCAP low dropout regulator. For cellular phones, PCMCIA cards, personal digital assistants (PDAs), DSP/ASIC suppliesGENERAL DESCRIPTIONADP3333 is a member of the ADP333x family of precision lowADP3333dropout anyCAP ..
ADP3333ARM-3.3-RL7 ,High Accuracy Ultralow IQ, 300 mA, anyCAP® Low Dropout Regulatorapplications. The ADP3333 achieves exceptionalaccuracy of ±0.8% at room temperature and ±1.8% overt ..
ADP3333ARM-5 ,High Accuracy Ultralow IQ, 300 mA, anyCAP Low Dropout RegulatorSPECIFICATIONSIN IN OUT JParameter Symbol Condition Min Typ Max UnitOUTPUT2Voltage Accuracy V V = V ..
AD8369ARU
45 dB Digitally Controlled VGA LF to 600 MHz
REV.0
45 dB Digitally Controlled VGA
LF to 600 MHz*Patents Pending
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Digitally Controlled Variable Gain in 3 dB Steps
–5 dB to +40 dB (RL = 1 k�)
–10 dB to +35 dB (RL = 200 �)
Less than 0.2 dB Flatness over a +20 MHz Bandwidth
up to 380 MHz
4-Bit Parallel or 3-Wire Serial Interface
Differential 200� Input and Output Impedance
Single 3.0 V–5.5 V Supply
Draws 37 mA at 5 V
Power-Down <1 mA Maximum
APPLICATIONS
Cellular/PCS Base Stations
IF Sampling Receivers
Fixed Wireless Access
Wireline Modems
InstrumentationOPHI and OPLO. The overall gain depends upon the source
and load impedances due to the resistive nature of the input and
output ports.
Digital control of the AD8369 is achieved using either a serial or
a parallel interface. The mode of digital control is selected by
connecting a single pin (SENB) to ground or the positive sup-
ply. Digital control pins can be driven with standard CMOS
logic levels.
The AD8369 may be powered on or off by a logic level applied
to the PWUP pin. For a logic high, the chip powers up rapidly
to its nominal quiescent current of 37 mA at 25ºC. When low,
the total dissipation drops to less than a few milliwatts.
The AD8369 is fabricated on an Analog Devices proprietary, high
performance 25 GHz silicon bipolar IC process and is available
in a 16-lead TSSOP package for the industrial temperature range
of –40∞C to +85∞C. A populated evaluation board is available.
PRODUCT DESCRIPTIONThe AD8369 is a high performance digitally controlled variable
gain amplifier (VGA) for use from low frequencies to a –3dB
frequency of 600 MHz at all gain codes. The AD8369 delivers
excellent distortion performance: the two-tone, third-order
intermodulation distortion is –69 dBc at 70 MHz for a 1 V p-p
composite output into a 1 kW load. The AD8369 has a nominal
noise figure of 7dB when at maximum gain, then increases with
decreasing gain. Output IP3 is +19.5 dBm at 70MHz into a
1 kW load and remains fairly constant over the gain range.
The signal input is applied to pins INHI and INLO. Variable gain
is achieved via two methods. The 6dB gain steps are implemented
using a discrete X-AMP® structure, in which the input signal is
progressively attenuated by a 200W R-2R ladder network that
also sets the input impedance; the 3dB steps are implemented at
the output of the amplifier. This combination provides very
accurate 3dB gain steps over a span of 45 dB. The output imped-
ance is set by on-chip resistors across the differential output pins,
AD8369–SPECIFICATIONS
(VS = 5 V, T = 25�C, RS = 200 �, RL = 1000 �, Frequency = 70 MHz, at maximum gain,
unless otherwise noted.)INPUT STAGE
POWER UP INTERFACE
AD8369
SPECIFICATIONS (Continued)
AD8369Specifications subject to change without notice.
SPECIFICATIONS (Continued)
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25∞C)Minimum Setup Time Data Enable vs. Clock (TES)2
TPW
CLOCK
DISABLED
DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB
(NOT TO SCALE)
TDHTDS
CLOCK
(BIT 1)
DATA
(BIT 0)
DATA
ENABLE
(DENB)Serial Programming Timing
PARALLEL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25∞C)Minimum Hold Time Data Enable vs. Data (TEH)2
Parallel Programming Timing
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8369 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VS, VPOS . . . . . . . . . . . . . . . . . . . . . . . .5.5 V
PWUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VS + 200 mV
BIT0, BIT1, BIT2, BIT3, DENB, SENB . . . . . .VS + 200 mV
Input Voltage, VINHI – VINLO . . . . . . . . . . . . . . . . . . . . . . . .4 V
Input Voltage, VINHI or VINLO with respect to COMM . .4.5 V
Input Voltage, VINHI – VINLO with respect to COMM
................................COMM – 200 mV
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .265 mW
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150∞C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125∞C
Operating Temperature Range . . . . . . . . . . . .–40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range (soldering 60 sec) . . . . . . .to 300∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Table I.Typical Voltage Gain vs. Gain Code (VS = 5 V, f = 70 MHz)
Gain
