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AD8362ARU-AD8362ARU-REEL7
50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector
50 Hz to 2.7 GHz
60 dB TruPwr™ Detector
Rev. B
FEATURES
Complete fully calibrated measurement/control system
Accurate rms-to-dc conversion from 50 Hz to 2.7 GHz
Input dynamic range of >60 dB: −52 dBm to +8 dBm in 50 Ω
Waveform and modulation independent:
(Such as GSM/CDMA/TDMA)
Linear-in-decibels output, scaled 50 mV/dB
Law conformance error of 0.5 dB
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V at 24 mA from −40°C to +85°C
Power-down capability to 1.3 mW
APPLICATIONS
Power amplifier linearization/control loops
Transmitter power control
Transmitter signal strength indication (TSSI)
RF instrumentation
FUNCTIONAL BLOCK DIAGRAM
BIAS
VOUT
VSET
PWDNCOMM
AD8362
INHI
INLO
VPOS
CLPF
CHPF
ACOM
DECL02923-B-001
Figure 1.
GENERAL DESCRIPTION The AD8362 is a true rms-responding power detector that has a
60 dB measurement range. It is intended for use in a variety of
high frequency communication systems and in instrumentation
requiring an accurate response to signal power. It is easy to use,
requiring only a single supply of 5 V and a few capacitors. It can
operate from arbitrarily low frequencies to over 2.7 GHz and
can accept inputs that have rms values from 1 mV to at least
1 V rms, with peak crest factors of up to 6, exceeding the
requirements for accurate measurement of CDMA signals.
The input signal is applied to a resistive ladder attenuator
that comprises the input stage of a variable gain amplifier.
The 12 tap points are smoothly interpolated using a proprietary
technique to provide a continuously variable attenuator, which
is controlled by a voltage applied to the VSET pin. The resulting
signal is applied to a high performance broadband amplifier. Its
output is measured by an accurate square-law detector cell. The
fluctuating output is then filtered and compared with the output
of an identical squarer, whose input is a fixed dc voltage applied
to the VTGT pin, usually the accurate reference of 1.25 V
provided at the VREF pin.
The difference in the outputs of these squaring cells is
integrated in a high gain error amplifier, generating a voltage at
the VOUT pin with rail-to-rail capabilities. In a controller
mode, this low noise output can be used to vary the gain of a
host system’s RF amplifier, thus balancing the set point against
the input power. Optionally, the voltage at VSET may be a
replica of the RF signal’s amplitude modulation, in which case
the overall effect is to remove the modulation component prior
to detection and low-pass filtering. The corner frequency of the
averaging filter may be lowered without limit by adding an
external capacitor at the CLPF pin. The AD8362 can be used to
determine the true power of a high frequency signal having a
complex low frequency modulation envelope (or simply as a
low frequency rms voltmeter). The high-pass corner generated
by its offset-nulling loop can be lowered by a capacitor added
on the CHPF pin.
Used as a power measurement device, VOUT is strapped to
VSET, and the output is then proportional to the logarithm of
the rms value of the input; that is, the reading is presented
directly in decibels and is conveniently scaled 1 V per decade,
that is, 50 mV/dB; other slopes are easily arranged. In controller
modes, the voltage applied to VSET determines the power level
required at the input to null the deviation from the setpoint.
The output buffer can provide high load currents.
The AD8362 is powered down by a logic high applied to the
PWDN pin, i.e., the consumption is reduced to about 1.3 mW. It
powers up within about 20 µs to its nominal operating current
of 20 mA at 25°C. The AD8362 is supplied in a 16-lead TSSOP
package for operation over the industrial temperature range of
−40°C to +85°C. An evaluation board is available.
TABLE OF CONTENTS Specifications...................................................................................3
Absolute Maximum Ratings..........................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Description.............................7
Equivalent Circuits..........................................................................8
Typical Performance Characteristics............................................9
Characterization Setup.................................................................14
Equipment...................................................................................14
Analysis........................................................................................14
Circuit Description........................................................................15
Square-Law Detection...............................................................15
Effect of Input Coupling on the Intercept Value....................16
Offset Elimination......................................................................16
Voltage vs. Power Calibration...................................................17
Effect of Signal Waveform.........................................................17
Operation at Low Frequencies..................................................17
Time-Domain Response of the Closed Loop.........................17
Alteration of the Internal Target Voltage.................................18
Effects at Each End of Dynamic Range...................................18
Input Protection..........................................................................19
Power-Enable Response Time..................................................19
Using the AD8362.........................................................................20
Basic Connections......................................................................20
Main Modes of Operation............................................................21
Operation in Measurement Modes.............................................22
Law Conformance Error............................................................22
Alternative Input Coupling Means..........................................23
Using a Narrow-Band Input Match.........................................23
Uncertainties in RIN and Power Calibration............................24
Choosing the Right Value for CHPF and CLPF.....................24
Use of Nonstandard Target Voltages........................................24
Adjusting the Intercept..............................................................25
Altering the Slope.......................................................................25
Envelope Elimination Mode.....................................................26
Operator in Controller Modes....................................................27
Use of an Input Balun................................................................27
General Applications....................................................................29
RMS Voltmeter with >100 dB Dynamic Range......................29
RF Power Meter with 80 dB Range..........................................30
High Slope Detectors Centered on a Narrow Window.........31
AD8362 Evaluation Board........................................................32
Outline Dimensions......................................................................34
Ordering Guide..........................................................................34
REVISION HISTORY
3/04—Data Sheet Changed from Rev. A to Rev. B. Updated Format.................................................................Universal
Changes to Specifications...............................................................3
Changes to the Offset Elimination Section................................16
Changes to the Operation at Low Frequencies Section............17
Changes to the Time-Domain Response of the Closed Loop
Section.............................................................................................17
Changes to Equation 13................................................................24
Changes to Table 5.........................................................................31
6/03—Data Sheet Changed from Rev. 0 to Rev. A. Updated Ordering Guide................................................................5
Change to Analysis Section..........................................................12
Updated AD8362 Evaluation Board Section.............................26
2/03—Revision 0: Initial Version SPECIFICATIONS VS = 5 V, T = 25°C, ZO = 50 Ω, differential input drive via Balun1, VTGT connected to VREF, VOUT tied to VSET, unless otherwise noted.
Table 1. 1 1:4 balun transformer, M/A-COM ETC 1.6-4-2-3. Resistive network consists of 33 Ω shunt and 25 Ω series.
3 See Figure 36.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTION
COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF02923-B
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions EQUIVALENT CIRCUITS
INHI
INLO
DECL
DECLB-003
Figure 3. Circuit A
VSET
ACOM
COMM
VPOS02923-B
Figure 4. Circuit B
VTGT
ACOM
COMM
VPOS
VTGT02923-B
Figure 5. Circuit C
CLPF02923-B
Figure 6. Circuit D
02923-B
Figure 7. Circuit E
TYPICAL PERFORMANCE CHARACTERISTICS –60
VOU
(V)
INPUT AMPLITUDE (dBm)02923-B
Figure 8. Output Voltage (VOUT) vs. Input Amplitude (dBm),
Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,
Sine Wave, Differential Drive
INPUT AMPLITUDE (dBm)
RROR IN VOUT (dB)
3.002923-B
Figure 9. Logarithmic Law Conformance vs. Input Amplitude
Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,
Sine Wave, Differential Drive
INPUT AMPLITUDE (dBm)
VO
(V
RROR IN VOUT (dB)02923-B
INPUT AMPLITUDE (dBm)
VOU
RROR IN VOUT (dB)
0.6
02923-B
Figure 11. VOUT and Law Conformance vs. Input Amplitude, Frequency
1900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C
INPUT AMPLITUDE (dBm)
VOU
RROR IN VOUT (dB)
0.602923-B
Figure 12. VOUT and Law Conformance vs. Input Amplitude, Frequency
2200 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C
INPUT AMPLITUDE (dBm)–60
VOU
–1002923-B
-013
INPUT AMPLITUDE (dBm)
RROR IN VOUT
(dB)
3.002923-B
Figure 14. Output Error from CW Linear Reference vs. Input Amplitude
with Different Waveforms, CW, IS95 Reverse Link, WCDMA 8-Channel,
WCDMA 15-Channel, Frequency 900 MHz
INPUT AMPLITUDE (dBm)
RROR IN VOUT
(dB)
–55–50–45–40–35–30–25–20–15–50510–1002923-B
Figure 15. Output Error from CW Linear Reference vs. Input Amplitude
with Different WCDMA Channel Loading, 4-Channel, 8-Channel,
15-Channel, Frequency 2200 MHz
INPUT AMPLITUDE (dBm)
RROR IN VOUT (dB)
3.002923-B
Figure 16. Output Error from CW Linear Reference vs. Input Amplitude,
3 Sigma to Either Side of Mean, with WCDMA 8-Channel,
WCDMA 15-Channel, Frequency 1900 MHz
INPUT AMPLITUDE (dBm)
RROR IN V
UT (dB)
3.002923-B
Figure 17. Output Error from CW Linear Reference vs. Input Amplitude,
3 Sigma to Either Side of Mean, with WCDMA 8-Channel,
15-Channel, Frequency 1900 MHz
02923-B
INPUT AMPLITUDE (dBm)
ROR IN V
UT (dB)
3.0
Figure 18. Output Error from CW Linear Reference vs. Input Amplitude,
3 Sigma to Either Side of Mean, with WCDMA 8-Channel,
WCDMA 15-Channel, Frequency 2200 MHz
INPUT AMPLITUDE (dBm)
(V
–1002923-B
Figure 19. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,
Sine Wave, Frequency 900 MHz, Part-to-Part Variation
INPUT AMPLITUDE (dBm)
VOU
–1002923-B
Figure 20. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,
Sine Wave, Frequency 1900 MHz, Part-to-Part Variation
INPUT AMPLITUDE (dBm)
RROR IN V
UT (dB)
–2.502923-B
Figure 21. Logarithmic Law Conformance vs. Input Amplitude,
3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz,
Temperature −40°C, +25°C, and +85°C
INPUT AMPLITUDE (dBm)
RROR IN V
UT (dB)
–2.502923-B
Figure 22. Logarithmic Law Conformance vs. Input Amplitude,
3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz,
Temperature −40°C, +25°C, and +85°C
INPUT AMPLITUDE (dBm)
RROR IN VOUT
(dB)
–2.502923-B
Figure 23. Logarithmic Law Conformance vs. Input Amplitude,
3 Sigma to Either Side of Mean, Sine Wave, Frequency 2200 MHz,
Temperature −40°C, +25°C, and +85°C
FREQUENCY (MHz)
SLOPE (
240025002600270002923-B
Figure 24. Logarithmic Slope vs. Frequency,
Temperature −40°C, +25°C, and +85°C
FREQUENCY (MHz)
INTE
RCE
T (dBm)–58
–6102923-B
Figure 25. Logarithmic Intercept vs. Frequency,
Temperature −40°C, +25°C, and +85°C
TEMPERATURE (°C)
CHANGE
IN S
(mV
3.002923-B
Figure 26. Change in Logarithmic Slope vs. Temperature, 3 Sigma to Either
Side of Mean, Frequencies 900 MHz, 1900 MHz, 2200 MHz
TEMPERATURE (°C)
CHANGE
IN INTE
RCE
T (dB)
2.002923-B
Figure 27. Change in Logarithmic Intercept vs. Temperature, 3 Sigma to
Either Side of Mean, Frequencies 900 MHz, 1900 MHz, 2200 MHz
SLOPE (mV/dB)
HITS
100534950515202923-B
Figure 28. Slope Distribution, Frequency 900 MHz
INTERCEPT (dBm)
HITS40
–61.0–58.0–60.5–60.0–59.5–59.0–58.502923-B
Figure 29. Logarithmic Intercept Distribution, Frequency 900 MHz
TIME (µs)0
RF BURS
T E
NABLE
(V
VOU02923-B
Figure 30. Output Response to RF Burst Input for Various
RF Input Levels, Carrier Frequency 900 MHz, CLPF = 0.1 µF
TIME (ms)0
RF BURS
T E
NABLE
(V
(V02923-B
Figure 31. Output Response to RF Burst Input for Various RF Input Levels,
Carrier Frequency 900 MHz, CLPF = 0.1 µF
TIME (µs)0
R-DOWN P
IN (V
VOU02923-B
Figure 32. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0
TIME (ms)0
R-DOWN P
IN (V
VOU02923-B
Figure 33. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0.1 µF
TIME (ms)0
R-DOWN P
IN (V
VOU02923-B
Figure 34. Output Response to Gating on Power Supply for Various RF Input
Levels, Carrier Frequency 900 MHz, CLPF = 0
180
210Figure 35. Input Impedance, ZO = 50 Ω, Differential Drive
TEMPERATURE (°C)
CHANGE
IN V
F (mV
–2502923-B
Figure 36. Change in VREF vs. Temperature, 3 Sigma to Either Side of Mean
VREF (V)
HITS
1.2301.2701.2351.2401.2451.2501.2601.2551.26502923-B
Figure 37. VREF Distribution
CHARACTERIZATION SETUP
EQUIPMENT The general hardware configuration used for most of the
AD8362 characterization is shown in Figure 38. The signal
source used was a Rohde & Schwarz SMIQ03B. A 1:4 balun
transformer was used to transform the single-ended RF signal
to differential form. For the response measurements in Figure
30 and Figure 31, the configuration shown in Figure 39 was
used; for Figure 32 and Figure 33, the configuration shown in
Figure 40 was used; and for Figure 34, the configuration shown
in Figure 41 was used.
02923-B-038
Figure 38. Primary Characterization Setup
ANALYSIS The slope and intercept are derived using the coefficients
of a linear regression performed on data collected in its
central operating range. Error is stated in two forms: error
from linear response to CW waveform and output delta
from 25°C performance.
The error from linear response to CW waveform is the
decibel difference in output from the ideal output defined by
the conversion gain and output reference. This is a measure of
the linearity of the device response to both CW and modulated
waveforms. The error in dB is calculated by
SlopeSlopeVOUTErrorIN−×−=dB
where PZ is the x intercept, expressed in dBm.
Error from the linear response to CW waveform is not a
measure of absolute accuracy since it is calculated using the
slope and intercept of each device. However, it verifies the
linearity and the effect of modulation on the device response.
Error from 25°C performance uses the performance of a given
device and waveform type as the reference; it is predominantly a
measurement of output variation with temperature.
02923-B-039
Figure 39. Response Measurement Setup for Modulated Pulse
02923-B-040
Figure 40. Response Measurement Setup for Power-Down Step
RF 50ΩFigure 41. Response Measurement Setup for Gated Supply
CIRCUIT DESCRIPTION The AD8362 is a fully calibrated, high accuracy, rms-to-dc
converter providing a measurement range of over 60 dB. It is
capable of operation from signals as low in frequency as a few
Hertz to at least 2.7 GHz. Unlike earlier rms-to-dc converters,
the response bandwidth is completely independent of the signal
magnitude. The −3 dB point occurs at about 3.5 GHz. The
capacity of this part to accurately measure waveforms having a
high peak-to-rms ratio (crest factor) is independent of either
the signal frequency or its absolute magnitude, over a wide
range of conditions.
This unique combination allows the AD8362 be to used with
equal ease as a calibrated RF wattmeter covering a power ratio
of >1,000,000:1, as a power controller in closed-loop systems, or
as a general-purpose rms-responding voltmeter, and in many
other low frequency applications.
INHI
INLO
CHPF
OFFSET
NULLING
VSET
VSET
VREF
VREF
1.25V
ACOM
VTGT
VOUTMATCH WIDE-
AMPLITUDE TARGETFOR VSIG02923-B
Figure 42. Basic Structure of the AD8362
The part comprises the core elements of a high performance
AGC loop (Figure 42), laser-trimmed during manufacture to
close tolerances while fully operational at a test frequency of
100 MHz. Its linear, wideband, variable gain amplifier (VGA)
provides a general voltage gain, GSET; this may be controlled in a
precisely exponential (linear-in-dB) manner over the full 68 dB
range from −25 dB to +43 dB by a voltage VSET. However, to
provide adequate guard-banding, only the central 60 dB of this
range, from −21 dB to +39 dB, is normally used. Later, it is
shown how this basic range may be shifted either up or down,
and even extended to >80 dB. The VGA gain has the form GNSOSETVSETGGexp (1)
where GO is a basic fixed gain and VGNS is a scaling voltage that
defines the gain slope (the dB change per volt). Note that the
gain decreases with VSET. The VGA output is GNSINOINSETSIGVGVGVexp (2)
where VIN is the ac voltage applied to the input terminals
of the AD8362.
As is later explained more fully, the input drive may be
either single-sided or differential but optimum performance at
input drive. The effect of HF imbalances when using a single-
sided drive is less apparent at low frequencies (from 50 Hz
to 500 MHz), but the peak input voltage capacity is always
halved relative to differential operation (see the Using the
AD8362 section).
SQUARE-LAW DETECTION The output of the variable-gain amplifier, VSIG, is
applied to a wideband square law detector, which provides a
true rms response to this alternating signal that is essentially
independent of waveform up to crest factors of 6. Its output
is a fluctuating current, ISQU, having a positive mean value. This
current is integrated by an on-chip capacitance, CF; this is
usually augmented by an external capacitance, CLPF, to extend
the averaging time. The resulting voltage is buffered by a gain-
of-5, dc-coupled amplifier whose rail-to-rail output, VOUT, may
be used either for measurement or control purposes.
In most applications, the AGC loop is closed via the setpoint
interface pin, VSET, to which the VGA gain-control voltage
VSET is applied. In measurement modes, the closure is direct
and local by a simple connection from the output the VOUT
pin to the VSET pin. In controller modes, the feedback path is
around some larger system, but the operation is the same.
The fluctuating current, ISQU, is balanced against a fixed setpoint
target current, ITGT, using current mode subtraction. With the
exact integration provided by the capacitor(s), the AGC loop
equilibrates when TGTSQUIMEAN (3)
The current ITGT is provided by a second-reference squaring
cell whose input is the amplitude-target voltage VATG. This is a
fraction of the voltage VTGT applied to a special interface that
accepts this input at the VTGT pin. Since the two squaring cells
are electrically identical and are carefully implemented in the
Accordingly, VTGT (and its fractional part VATG) determines the
output that must be provided by the VGA for the AGC loop to
settle. Since the scaling parameters of the two squarers are
accurately matched, it follows that Equation 3 is satisfied only
when 22
ATGSIGVVMEAN= (4)
In a formal solution, one would then extract the square root of
both sides to provide an explicit value for the root-mean-square
(rms) value. However, it is apparent that by forcing this identity,
through varying the VGA gain and extracting the mean value
by the filter provided by the capacitor(s), the system inherently
establishes the relationship ATGSIGVrms= (5)
Substituting the value of VSIG from Equation 2, we have ATGGNSINOVVSETVrms=exp (6)
As a measurement device, VIN is the unknown quantity and all
other parameters can be fixed by design. Solving Equation 6: GNSATGINOVrmsexp (7)
so ZINGNSVVVSETlog= (8)
The quantity VZ = VATG/GO is defined as the intercept voltage
because VSET must be 0 when rms (VIN) = VZ.
When connected as a measurement device, the output of the
buffer is tied directly to VSET, which closes the AGC loop.
Making the substitution VOUT = VSET and changing the log
base to 10, as needed in a decibel conversion, we have ZINSLPVVVOUT10log= (9)
where VSLP is the slope voltage, that is, the change in output
voltage for each decade of change in the input amplitude.
(Note that VSLP = VGNS log (10) = 2.303 VGNS). In the AD8362,
VSLP is laser trimmed to 1 V using a 100 MHz test signal.
Because a decade corresponds to 20 dB, this slope may also be
stated as 50 mV/dB. It is later shown how the effective value of
VSLP may be altered by the user.
Likewise, the intercept VZ is also laser trimmed to 316 µV
(−70 dBV). In an ideal system, VOUT would cross zero for an
rms input of that value. In a single-supply realization of the
function, VOUT cannot run fully down to ground; here, VZ is
the extrapolated value. In measurement modes, the output
ranges from 0.5 V for VIN = 1 mV (input values are stated as
rms, outputs values as dc), up to a voltage 60 dB × 50 mV/dB =
RMS INPUT VOLTAGE (100µV TO 3.2V)100µV
1mV10mV100mV1V10V
4.002923-B
Figure 43. Ideal Response of the AD8362
EFFECT OF INPUT COUPLING ON THE INTERCEPT
VALUE Reductions of VIN due to coupling losses directly affect VZ. In
high frequency applications, several factors contribute to the
coupling of the source into the IC, including the board and
package resonances and attenuation. Any uncertainties in the
input impedance result in the intercept expressed in power
terms, which is nominally −57 dBm for a 50 Ω system, being
less accurately determined than when stated in dBV (that is, in
pure voltage) terms. On the other hand, the slope VSLP is
unaffected by all such impedance or coupling uncertainties.
OFFSET ELIMINATION To address the small dc offsets that arise in the variable gain
amplifier, an offset-nulling loop is used. The high-pass corner
frequency of this loop is internally preset to 1 MHz, sufficiently
low for most HF applications. When using the AD8362 in LF
applications, the corner frequency can be reduced as needed by
the addition of a capacitor from the CHPF pin to ground having
a nominal value of 200 µF/Hz. For example, to lower the high-
pass corner frequency to 150 Hz, a capacitance of 1.33 µF is
required. The offset voltage varies depending on the actual gain
at which the VGA is operating, and thus, on the input signal
amplitude.
Baseline variations of this sort are a common aspect of all
VGAs, although more evident in the AD8362 because of the
method of its implementation, which causes the offsets to
ripple along the gain axis with a period of 6.33 dB. When an
excessively large value of CHPF is used, the offset correction
process may lag the more rapid changes in the VGA’s gain,
which may increase the time required for the loop to fully settle
for a given steady input amplitude.
VOLTAGE VS. POWER CALIBRATION The AD8362 can be used as an accurate rms voltmeter
from arbitrarily low frequencies to microwave frequencies.
For low frequency operation, the input is usually specified
either in volts rms or in dBV (decibels relative to 1 V rms).
Driven differentially, the specified input range in dBV runs
from −60 dBV to 0 dBV (1 mV to 1 V rms). In these terms,
the intercept is at −70 dBV.
At high frequencies, signal levels are commonly specified
in power terms. In these circumstances, the source and
termination impedances are an essential part of the overall
scaling. To set the AD8362’s input impedance to 50 Ω, it is
necessary to add a resistor of 66.7 Ω across the internal 200 Ω
differential input impedance of the IC. (This is discussed
further in later sections.) For this condition, the intercept
occurs at a nominal power level of −57 dBm, and VOUT
can be stated in this way: mV5057+=INVOUT (10)
where PIN is expressed in dBm. For example, an input of
−30 dBm generates an output of 1.35 V.
EFFECT OF SIGNAL WAVEFORM The measurement accuracy of an rms-responding device is
ideally unaffected by the waveform of the input signal. This is a
valuable asset in wideband CDMA systems and in many other
modulation modes where there is a significant amount of
random variation of the RF carrier amplitude at baseband
frequencies. The high accuracy of the AD8362 in such cases is
indicated by the Typical Performance Characteristics graphs
and in the Specifications table. Note that at low frequencies, it is
customary to provide a specification of measurement errors due
to waveform effects as a function of the crest factor (σ) rather
than in terms of a system-specific modulation mode.
When measuring signals whose waveforms have high but
brief peak values (that is, having high crest factors), these
peaks may be clipped, causing a reduction in the apparent value
of the input being measured. This issue is discussed further in
connection with the detailed description of the input system.
OPERATION AT LOW FREQUENCIES In conventional rms-to-dc converters based on junction
techniques, the effective signal bandwidth is proportional to the
signal amplitude. For a 1 MHz rms-to-dc converter, this is the
full-scale bandwidth. However, at an input 60 dB below full-
scale, the bandwidth could be as low as 1 kHz. In sharp contrast,
the 3.5 GHz bandwidth of the VGA in the AD8362 is
independent of its gain. Since this amplifier is internally dc-
coupled, the system can also be used as a high accuracy rms
voltmeter at low frequencies, retaining its temperature-stable
In such cases, the input coupling capacitors should be large
enough so that the lowest frequency components of the signal
that are to be included in the measurement are minimally
attenuated. For example, for a 3 dB reduction at 1.5 kHz,
capacitances of 1 µF are needed because the input resistance is
100 Ω at each input pin (200 Ω differentially) and we calculate
1/(2π × 1.5 kΩ × 100) = 1 µF. Also, to lower the high-pass
corner frequency of the VGA, a capacitor of value 200 µF-Hz
should be used between the CHPF pin and ground; to provide a
similar 1.5 kHz high-pass corner, a capacitor of 133 nF should
be used.
TIME-DOMAIN RESPONSE OF THE CLOSED LOOP The external low-pass averaging capacitance, CLPF, added at
the output of the squaring cell, is chosen to provide adequate
filtering of the fluctuating detected signal. The optimum value
depends on the application; as a guideline, a value of roughly
900 µF-Hz should be used. For example, a capacitance of 5 µF
provides adequate filtering down to 180 Hz. Note that the
fluctuation in the quasi-dc output of a squaring cell operating
on a sine wave input is a raised cosine at twice the signal
frequency, easing this filtering function.
In the standard connections for the measurement mode,
the VSET pin is tied to VOUT. For small changes in input
amplitude (a few decibels), the time-domain response of this
loop is essentially linear, with a 3 dB low-pass corner frequency
of nominally fLP = 1/(CLPF × 1.1 kΩ). Internal time delays
around this local loop set the minimum recommended value of
this capacitor to about 300 pF, giving fLP = 3 MHz.
When large and abrupt changes of input amplitude occur,
the loop response becomes nonlinear and exhibits slew rate
limitations. Further, due to the fundamentals of a system using
transconductance squaring cells as employed in the AD8362,
the slewing is asymmetric for increasing and decreasing inputs.
Figure 44 shows typical waveforms for VOUT for three values
of VIN using CLPF = 1 nF.
TIME (µs)
V
(V02923-B
-044
The most satisfactory way to quantify slew-rate limitations is by
considering the peak currents that can be generated by the
squaring cells. During a fast increase in input level, the peak
current into the integrating (loop filter) capacitance, CLPF, is
approximately 2.5 mA. The actual value depends on several
factors, including the size of the step, and extremes in chip
temperature. The voltage across the 1 nF capacitor thus
increases at a rate of nominally 2.5 V/µs. Because the output
buffer has a gain of 5, the output slew rate is 12.5 V/µs. The peak
rate persists up to a point about 10 dB below the final value,
after which the response gradually converges on the linear
system response, as noted previously.
On the other hand, during a fast decrease in input level, the
peak current in CLPF in the opposite (discharging) direction is
much smaller; it is roughly 25 µA. Thus, the slew rate for VOUT
in the descending direction is only about 0.125 V/µs for CLPF =
1 nF. Discharging over the full 3 V range (a 60 dB reduction of
input) requires a time interval of ~24 µs. These figures are
verified in the results shown in Figure 44.
ALTERATION OF THE INTERNAL TARGET VOLTAGE The AD8362 incorporates several features that extend its
versatility. One of these is the ability to alter the target
voltage. As noted, the output of the VGA is forced to a
value set by the internal bias voltage (VATG = 0.06 × VTGT)
applied to the reference squaring cell. It is normally set to 75
mV dc by connecting VTGT to the 1.25 V reference voltage at
the VREF pin. However, it may optionally be varied from 0 V
up to ±0.24 V (±4 V at VTGT). Note that the sign of this input
is unimportant, because it is internally squared.
By lowering VATG, the output of the VGA needed to balance the
output currents of the two matched squaring cells is similarly
lowered. This reduces the intercept in precisely the same ratio.
Thus, if we halve the setpoint target voltage by halving the
voltage applied to the VTGT pin, the intercept moves to the left
(to a smaller input level) by 6.02 dB. This effectively doubles the
measurement system’s sensitivity.
Furthermore, because the signal amplitude needed to drive the
squaring cell is halved, the output stage of the VGA now has
twice the dynamic headroom (before clipping) and can handle
waveforms having crest factors that are twice as large. Figure 45
shows the overall response for an illustrative set of values of
VTGT = 0.3 V, 0.533 V, 0.949 V, 1.687 V, and 3.0 V. While this is
usually a fixed dc voltage, it can also be a time-varying, unipolar
or bipolar voltage, in which case the overall operation is rather
more complex. For example, when VTGT is derived from
VOUT, the dynamic range can be extended to over 80 dB.
Examples of such uses of this feature are presented later.
RMS INPUT VOLTAGE (V)
RELATIVE INTERCEPT (dB)100µ1m10m10
OUTPUT VOLTAGE (V)
0.1102923-B
Figure 45. Response with VTGT Varied from 0.3 V to 3 V in 5 dB Steps,
Showing the Proportional Shift in Intercept
EFFECTS AT EACH END OF DYNAMIC RANGE All AGC loops have a limited minimum and maximum input
beyond which the system cannot respond correctly. However,
the output of a well-behaved system is in error in such a way as
to avoid anomalous measurements. For an input below its
minimum capability, the output should not turn around to
falsely indicate a higher input value; for inputs above its
maximum capability, the output should not fold over and return
to some lower value.
The actual behavior of the AD8362 under these conditions can
be seen in the set of plots in Figure 45, the lower panel of which
shows the deviation from the ideal response with a slope of
50 mV/dB. For inputs below a certain level corresponding to the
point at which the VGA is operating at its maximum gain, its
output can no longer meet the rms amplitude target set by
VTGT, so the output moves quickly to its minimum value in an
attempt to provide the needed extra gain. As VTGT is altered,
the corresponding end-limit voltage moves to the left or to the
right.
On the other hand, when the input is above a certain upper
limit where the VGA gain has been driven to its minimum
gain, any further increase drives its output well above the target
voltage needed to balance the loop. The resulting integration of
this internal error signal causes VOUT to rise abruptly. In either
case, this output takes on a safe value and does not fold back
under any conditions.
The dynamic range, the “dB distance” between these limits, is
not basically dependent on VTGT. The middle line in the plots
of Figure 45 (VTGT = 0.949 V) extends from 0.5 mV to 1.5 V
between the ±1% error points; the dynamic range is thus
slightly over 68 dB. For other values of VTGT, this basic 68 dB
range just moves to the left or to the right.
