AD8349ARE Fast Delivery |IC PHOENIX CO.,LIMITED

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AD8349ARE
700 MHz to 2700 MHz Quadrature Modulator
700 MHz to 2700 MHz
Quadrature Modulator
Rev. 0
FEATURES
Output frequency range: 700 MHz to 2700 MHz
Modulation bandwidth: dc to 160 MHz (large signal BW)
1 dB output compression: 5.6 dBm @ 2140 MHz
Output disable function: output below –50 dBm in < 50 ns
Noise floor: –156 dBm/Hz
Phase quadrature error: 0.3 degrees @ 2140 MHz
Amplitude balance: 0.1 dB
Single supply: 4.75 V to 5.25 V
Pin compatible with AD8345/AD8346
16-lead exposed-paddle TSSOP package
APPLICATIONS
Cellular/PCS communication systems infrastructure
WCDMA/CDMA2000/PCS/GSM/EDGE
Wireless LAN/wireless local loop
LMDS/broadband wireless access systems
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
LOIN
QBBP
QBBN
COM3
COM3
VPS2
LOIP
VPS1
ENOP
VOUT
COM3
COM2
Figure 1
PRODUCT DESCRIPTION
The AD8349 is a silicon, monolithic, RF quadrature modulator
that is designed for use from 700 MHz to 2700 MHz. Its
excellent phase accuracy and amplitude balance enable high
performance direct RF modulation for communication systems.
The differential LO input signal is buffered, and then split into
an in-phase (I) signal and a quadrature-phase (Q) signal using a
polyphase phase splitter. These two LO signals are further
buffered and then mixed with the corresponding I channel and
Q channel baseband signals in two Gilbert cell mixers. The
mixers’ outputs are then summed together in the output
amplifier. The output amplifier is designed to drive 50 Ω loads.
The RF output can be switched on and off within 50 ns by
applying a control pulse to the ENOP pin.
The AD8349 can be used as a direct-to-RF modulator in digital
communication systems such as GSM, CDMA, and WCDMA
base stations, and QPSK or QAM broadband wireless access
transmitters. Its high dynamic range and high modulation
accuracy also make it a perfect IF modulator in local multipoint
distribution systems (LMDS) using complex modulation
formats.
The AD8349 is fabricated using Analog Devices’ advanced
complementary silicon bipolar process, and is available in a 16-
lead exposed-paddle TSSOP package. Its performance is
specified over a –40°C to +85°C temperature range.
TABLE OF CONTENTS
Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Pin Configuration and Functional Descriptions..........................6
Equivalent Circuits...........................................................................7
Typical Performance Characteristics.............................................8
Circuit Description.........................................................................14
Overview......................................................................................14
LO Interface.................................................................................14
V-to-I Converter.........................................................................14
Mixers..........................................................................................14
D-to-S Amplifier.........................................................................14
Bias Circuit..................................................................................14
Output Enable.............................................................................14
Basic Connections..........................................................................15
Baseband I and Q Inputs...........................................................15
Single-Ended Baseband Drive..................................................15
LO Input Drive Level.................................................................16
Frequency Range........................................................................16
LO Input Impedance Matching................................................16
Single-Ended LO Drive..............................................................17
RF Output....................................................................................17
Output Enable.............................................................................17
Baseband DAC Interface...........................................................18
AD9777 Interface.......................................................................18
Biasing and Filtering..................................................................18
Reducing Undesired Sideband Leakage..................................18
Reduction of LO Feedthrough.................................................19
Sideband Suppression and LO Feedthrough Versus
Temperature................................................................................19
Single Sideband Performance versus Baseband Drive Level20
Improving Third Harmonic Distortion...................................20
Applications.....................................................................................21
3GPP WCDMA Single-Carrier Application...........................21
WCDMA MultiCarrier Application........................................21
GSM/EDGE Application...........................................................22
Soldering Information...............................................................23
LO Generation Using PLLs.......................................................23
Transmit DAC Options.............................................................23
Evaluation Board............................................................................24
Characterization Setups.................................................................26
SSB Setup.....................................................................................26
Outline Dimensions.......................................................................27
Ordering Guide..........................................................................27
REVISION HISTORY
Revision 0: Intitial Version
SPECIFICATIONS
Table 1. VS = 5 V; Ambient Temperature (TA) = 25°C; LO = –6 dBm; I/Q inputs = 1.2 V p-p differential sine waves in quadrature on
a 400 mV dc bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω, unless otherwise noted.

1 The amplitude of the third harmonic relative to the single sideband power decreases with decreasing baseband drive level (see Figure 19, Figure 20, and Figure 21).
ABSOLUTE MAXIMUM RATINGS
Table 2. AD8349 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
IBBP
IBBN
COM1
COM1
LOIN
QBBP
QBBN
COM3
COM3
VPS2
LOIP
VPS1
ENOP
VOUT
COM3
COM2
03570-0-002
Figure 2
Table 3. Pin Function Descriptions
EQUIVALENT CIRCUITS
VPS2
IBBP
COM3
03570-0-003
Figure 3. Circuit A
VPS1
LOIN
LOIP
COM1
Figure 4. Circuit B
VPS2
ENOP
COM3
Figure 5. Circuit C
VOUT
COM2
VPS2
Figure 6. Circuit D
TYPICAL PERFORMANCE CHARACTERISTICS
OUTP
UT P
R (dBm)4
LO FREQUENCY (MHz)
Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO)
(I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz,
I and Q Inputs at 1.2 V p-p Differential, TA = 25°C)
OUTP
UT P
R V
ARIATION (dB)
03570-0-008BASEBAND FREQUENCY (MHz)101000100
Figure 8. I and Q Input Bandwidth Normalized to Gain @ 1 MHz
(FLO = 1500 MHz, TA = 25°C)
OUTP
UT P
R (dBm)
TEMPERATURE (°C)507080
1dB
OU
TPU
ESSION
LO FREQUENCY (MHz)
Figure 10. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
CARRIE
FE
THROUGH (dBm)
LO FREQUENCY (MHz)
Figure 11. Carrier Feedthrough vs. FLO (FBB = 1 MHz, I and Q Inputs Driven in
Quadrature at 1.2 V p-p Differential, TA = 25°C)
CARRIE
FE
THROUGH (dBm)
TEMPERATURE (°C)507080
03570-0-012
SIDEBAND SUPPRESSION (dBc)
LO FREQUENCY (MHz)
Figure 13. Sideband Suppression vs. FLO (FBB = 1 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
IDE
BAND S
ION (dBc
BASEBAND FREQUENCY (MHz)10100
Figure 14. Sideband Suppression vs. FBB (FLO = 2140 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
SIDEBAND SUPPRESSION (dBc)
TEMPERATURE (°C)507080
Figure 15. Sideband Suppression vs. Temperature (FLO = 2140 MHz,
FBB = 1 MHz, I and Q Inputs Driven in Quadrature 1.2 V p-p Differential)
THIRD ORDE
R DIS
ORTION (dBc
LO FREQUENCY (MHz)
Figure 16. Third Order Distortion vs. FLO (FBB = 1 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
THIRD ORDE
R DIS
ORTION (dBc
BASEBAND FREQUENCY (MHz)10100
Figure 17. Third Order Distortion vs. FBB (FLO = 2140 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
THIRD ORDE
R DIS
ORTION (dBc
TEMPERATURE (°C)507080
Figure 18. Third Order Distortion vs. Temperature (FLO = 2140 MHz,
FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential)
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
2.2
Figure 19. Third Order Distortion (3USB), Carrier Feedthrough, Sideband
Suppression, and SSB POUT vs. Baseband Differential Input Level
(FLO = 900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
2.2
Figure 20. Third Order Distortion (3USB), Carrier Feedthrough, Sideband
Suppression, and SSB POUT vs. Baseband Differential Input Level
(FLO = 1900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
2.2
Figure 21. Third Order Distortion (3USB), Carrier Feedthrough, Sideband
CURRE
NT (mA)140
TEMPERATURE (°C)507080
Figure 22. Power Supply Current vs. Temperature
Figure 23. Smith Chart of LOIP Port S11 (LOIN Pin AC-Coupled
to Ground) Curves with Balun and External Termination
Resistors Also Shown (TA = 25°C)
TURN LOS
(dB)
FREQUENCY (MHz)
Figure 24. Return Loss ⏐S22⏐of VOUT Output (TA = 25°C)
RCE
NTAGE
–157.0–155.5–155.0–154.5–154.0–153.5–153.0–156.0–156.5NOISE FLOOR (dBm/Hz)
03570-0-025
Figure 25. 20 MHz Offset Noise Floor Distribution at FLO = 900 MHz
(I and Q Inputs at a Bias of 400 mV, TA = 25°C)
RCE
NTAGE
–158.0–156.5–156.0–155.5–155.0–154.5–154.0–157.0–157.5NOISE FLOOR (dBm/Hz)
Figure 26. 20 MHz Offset Noise Floor Distribution at FLO = 1900 MHz
(I and Q Inputs at a Bias of 400 mV, TA = 25°C)
RCE
NTAGE
–159.0–157.5–157.0–156.5–156.0–155.5–155.0–158.0–158.5NOISE FLOOR (dBm/Hz)
Figure 27. 20 MHz Offset Noise Floor Distribution at FLO = 2140 MHz
RCE
NTAGE
NOISE FLOOR (dBm/Hz)
Figure 28. 20 MHz Offset Noise Floor Distribution at FLO = 940 MHz
(FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
RCE
NTAGE
–152.5–151.5–151.0–150.5–150.0–149.5–149.0–148.5–152.0–148.0NOISE FLOOR (dBm/Hz)
03570-0-029
Figure 29. 20 MHz Offset Noise Floor Distribution at FLO = 1960 MHz
(FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
RCE
NTAGE
152.5NOISE FLOOR (dBm/Hz)
Figure 30. 20 MHz Offset Noise Floor Distribution at FLO = 2140 MHz
NOIS
FLOOR (dBm/Hz)
LO INPUT (dBm)
–102
03570-0-031–6–4–20
Figure 31. 20 MHz Offset Noise Floor vs. LO Input Power
(FLO = 2140 MHz, TA = 25°C)
CARRIE
FE
THROUGH (dBm)
LO INPUT (dBm)
Figure 32. Carrier Feedthrough vs. LO Input Power (FBB = 1 MHz, I and Q
Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
SIDEBAND SUPPRESSION (dBc)
LO INPUT (dBm)
Figure 33. Sideband Suppression vs. LO Input Power (FBB = 1 MHz, I and Q
Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
RCE
NTAGE
MAGNITUDE IMBALANCE (dB)
03570-0-034
Figure 34. I and Q Inputs Quadrature Phase Imbalance Distribution
(FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in
Quadrature at 1.2 V p-p Differential, TA = 25°C)
RCE
NTAGE
PHASE (I-Q) IMBALANCE (Degrees)
03570-0-035
Figure 35. I and Q Inputs Amplitude Imbalance Distribution
(FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in
Quadrature at 1.2 V p-p Differential, TA = 25°C)
RCE
NTAGE
OP1dB (dBm)
5.04.55.56.06.5
03570-0-036
Figure 36. OP1dB Distribution. (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
RCE
NTAGE
CARRIER FEEDTHROUGH (dBm)
–55–50
Figure 37. Carrier Feedthrough Distribution at FLO = 1900 MHz (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 Vp-p, TA = 25°C)
CARRIER FEEDTHROUGH (dBm)
RCE
NTAGE
–70–65–60–55–50–45–40–35–30
Figure 38. Carrier Feedthrough Distribution at FLO = 2140 MHz (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
RCE
NTAGE
CARRIER FEEDTHROUGH (dBm)
Figure 39. Carrier Feedthrough Distribution at FLO = 900 MHz. (FBB = 1 MHz, I
and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
RCE
NTAGE
–70–65–60–55–50–45CARRIER FEEDTHROUGH (dBm)
AFTER NULLING TO <–65dBm AT +25°C
03570-0-037
Figure 40. Carrier Feedthrough Distribution at Temperature Extremes, After
Carrier Feedthrough Nulled to < - 65 dBm at TA = 25°C. (FLO = 2140 MHz,
I and Q Inputs at a bias of 400 mV)
RCE
NTAGE
–75–65–60–55–50–35SIDEBAND SUPPRESSION (dBc)
AFTER NULLING TO <–50dBc AT +25°C
–70–40–45
Figure 41. Sideband Suppression Distribution at Temperature Extremes, After
Sideband Suppression Nulled to < -50 dBc at TA = 25°C. (FLO = 2140 MHz,
FBB = 1 MHz, I and Q Inputs biased at 0.4 V)
CIRCUIT DESCRIPTION
OVERVIEW
The AD8349 can be divided into five sections: the local oscil-
lator (LO) interface, the baseband voltage-to-current (V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 42.
OUT
LOIP
LOIN
IBBP
IBBN
QBBP
QBBN
03570-0-043
Figure 42. AD8349 Block Diagram
The LO interface generates two LO signals at 90 degrees of
phase difference to drive two mixers in quadrature. Baseband
signals are converted into currents by the V-to-I converters,
which feed into the two mixers. The outputs of the mixers
combine to feed the differential-to-single-ended amplifier,
which provides a 50 Ω output interface. Reference currents to
each section are generated by the bias circuit. Additionally, the
RF output is controlled by an output enable pin (ENOP), which
is capable of switching the output on and off within 50 ns. A
detailed description of each section follows.
LO INTERFACE
The LO interface consists of interleaved stages of buffer
amplifiers and polyphase phase splitters. An input buffer
provides a 50 Ω termination to the LO signal source driving
LOIP and LOIN. The buffer also increases the LO signal
amplitude to drive the phase splitter. The phase splitter is
formed by an R-C polyphase network that splits the buffered
LO signal into two parts in precise quadrature phase relation
with each other. Each LO signal then passes through a buffer
amplifier to compensate for the signal loss through the phase
splitter. The two signals pass through another polyphase
network to enhance the quadrature accuracy over the full
operating frequency range. The outputs of the second phase
splitter are fed into the driver amplifiers for the mixers’ LO
inputs.
V-TO-I CONVERTER
The differential baseband input voltages that are applied to the
baseband input pins are fed to two op amps that perform a
differential voltage-to-current conversion. The differential
output currents of these op amps then feed each of their
respective mixers.
MIXERS
The AD8349 has two double-balanced mixers, one for the in-
phase channel (I channel) and one for the quadrature channel
(Q channel). Both mixers are based on the Gilbert cell design of
four cross-connected transistors. The output currents from the
two mixers sum together in a pair of resistor-inductor (R-L)
loads. The signals developed across the R-L loads are sent to the
D-to-S amplifier.
D-TO-S AMPLIFIER
The output D-to-S amplifier consists of two emitter followers
driving a totem pole output stage. Output impedance is estab-
lished by the emitter resistors in the output transistors. The
output of this stage connects to the output (VOUT) pin.
BIAS CIRCUIT
A band gap reference circuit generates the proportional-to-
absolute-temperature (PTAT) reference currents used by
different sections. The band gap reference circuit also generates
a temperature stable current in the V-to-I converters to produce
a temperature independent slew rate.
OUTPUT ENABLE
During normal operation (ENOP = high), the output current
from the V-to-I converters feeds into the mixers, where they
mix with the two phases of LO signals. When ENOP is pulled
low, the V-to-I output currents are steered away from the
mixers, thus turning off the RF output. Power to the final stage
of LO drivers is also removed to minimize LO feedthrough.
Even when the output is disabled, the differential-to-single-
ended stage is still powered up to maintain constant output
impedance.

Partno	Mfg	Dc	Qty	Available	Descript
AD8349ARE	ADI	N/a	500	avai	700 MHz to 2700 MHz Quadrature Modulator