AD8348ARU ,50?000 MHz quadrature demodulatorGeneral Description The AD8348 is a broadband quadrature demodulator with an Separate I & Q-chann ..
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AD8348ARU
50?000 MHz quadrature demodulator
PRELIMINARY TECHNICAL DATA
Rev. PrF 2/11/03
50–1000 MHza
Quadrature Demodulator
Features
Integrated I/Q demodulator with IF VGA Amplifier
Operating IF Frequency 50–1000 MHz (3dB IF BW of 500MHz driven from Rs=200ohms)
Demodulation Bandwidth 60MHz
Linear-in-dB AGC Range 45dB
Third Order Intercept
IIP3 +26 dBm @ min gain (FIF=450MHz)
IIP3 -7 dBm @ max gain (FIF=450MHz)
Quadrature Demodulation Accuracy
Phase Accuracy 0.6o RMS
Amplitude Balance 0.3 dB
Noise Figure 12.5dB @ max gain (FIF=500MHz)
LO Input -10 dBm
Single Supply 2.7-5.5V
Power down mode
Compact 28-pin TSSOP package Applications
QAM/QPSK Demodulator
W-CDMA/CDMA/GSM/NADC
Wireless Local Loop
LMDS/MMDS General Description The AD8348 is a broadband quadrature demodulator with an
integrated intermediate frequency (IF) variable-gain amplifier (VGA) and integrated baseband amplifiers. It is suitable for
use in communications receivers, performing quadrature
demodulation from IF directly to baseband frequencies. The baseband amplifiers have been designed to directly interface
with dual channel A-to-D converters such as the AD9201,
AD9283, and AD9218 for digitizing and post-processing. The IF input signal is fed into two Gilbert-cell mixers through
an X-AMP VGA. The IF VGA provides 45dB of gain
control. A precision gain-control circuit sets a linear-in-dB gain characteristic for the VGA and provides temperature
compensation. The LO quadrature phase splitter employs a
divide-by-two frequency divider to achieve high quadrature accuracy and amplitude balance over the entire operating fre-
quency range.
Optionally, the IF VGA can be disabled and bypassed. In this mode, the IF signal is applied directly to the quadrature mixer
inputs via pins MXIP and MXIN.
Functional Block Diagram Separate I & Q-channel baseband amplifiers follow the
baseband outputs of the mixers. The DC common-mode
voltage level at the baseband outputs is set by the voltage applied to the VCMO pin. Typically VCMO is connected to
the internal VREF voltage but it can also be connected to an
external voltage. This flexibility allows the user to maximize the input dynamic range to the A-to-D converter. Connecting
a bypass capacitor at each offset compensation input (IOFS &
QOFS) nulls DC offsets produced in the mixer. Offset compensation can be overridden by applying an external
voltage at the offset compensation inputs.
The mixers’ outputs are brought off-chip for optional filtering before final amplification. Inserting a channel selection filter
before each baseband amplifier increases the baseband
amplifiers’ signal handling range by reducing the amplitude of high-level, out-of-channel interferers before the baseband
signal is fed into the baseband amplifiers. The single-ended
mixer output is amplified and converted to a differential signal for driving ADCs.
PRELIMINARY TECHNICAL DATA
AD8348-SPECIFICATIONS (VS = 5V; TA=25 °
C; FLO=500MHz; FIF=501MHz; Plo=-10dBm, Rs(LO)= 50 Ω, Rs(IF)=200Ω,
unless otherwise noted)
PRELIMINARY TECHNICAL DATA PRELIMINARY TECHNICAL DATA Specifications subject to change without notice.
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS* Supply Voltage VPS1, VPS2, VPS3……..…….5.5V
LO & RF Input Power …………..…….…TBD dBm
Internal Power Dissipation ….…..……..….…..TBD
θJA ……………………………………….TBD C/W
Maximum Junction Temperature ……..…+TBD° C
Operating Temperature Range ….-40° C to +85° C
Storage Temperature Range …...-65° C to +150° C
Lead Temperature (Soldering 60 sec)..….+TBD° C
*Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATION C A U T I O N E S D ( e l e c t r o s t a t i c d i s c h a r g e ) s e n s i t i v e d e v ice. Electrostatic charges as high as 4000 V readilyc c u m u l a t e o n t h e h u m a n b o d y a n d t e s t e q uipment and can discharge without detection. Altho u g h h e 8 3 4 8 f e a t u r e s p r o p r i e t a r y E S D p r o t e ction circuitry, permanent damage may occur one v i c e s s u b c t e d t o h i g h e n e r g y [ > 2 5 0 V H BM] electrostatic discharges. Therefore, proper ESD r e c a u t i o n s a r e r e c o m m e n d e d t o a v o i d p e r formance degradation or loss of functionality.DEVICE
ORDERING GUIDE PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTIONS PRELIMINARY TECHNICAL DATA
Theory of operation
VGA The VGA is implemented using the patented X-AMP architecture. The single-ended IF signal is attenuated in eight
discrete 6-dB steps by a passive R-2R ladder. Each discrete
attenuated version of the IF signal is applied to the input of a transconductance stage. The current outputs of all
transconductance stages are summed together and drive a
resistive load at the output of the VGA. Gain control is achieved by smoothly turning on and off the relevant
transconductance stages with a temperature-compenstated
interpolation circuit. This scheme allows the gain to
continuously varied over a 48dB range with linear-in-dB gain control. This configuration also keeps the relative dynamic
range constant (e.g. IIP3-NF in dB) over gain setting. The
absolute intermodulation intercepts and noise figure, however, vary directly with gain. The analog voltage VGIN sets the
gain. VGIN=0V is the maximum gain setting, and
VGIN=1.2V is the minimum voltage gain setting.
Downconversion mixers The output of the VGA drives two (I & Q) double-balanced
Gilbert-cell down-conversion mixers. Alternatively, the VGA can be disabled by driving the ENVG pin low and the
mixers can be driven directly externally via the MXIP, MXIN
port. At the input of the mixer, a degenerated differential pair performs linear voltage-to-current conversion. The
differential output current feeds into the mixer core where it is
downconverter by the mixing action of the Gilbert cell. The
phase splitter provides quadrature LO signals which drive the LO ports of the in- phase and quadrature mixers.
Buffers at the output of each mixer drive pins IMXO and QMXO respectively. These linear, low-output impedance
buffers drive 40ohm temperature-stable, passive resistors in
series with each of the output pins (IMXO, QMXO). This 40ohms should be considered when calculating the reverse
termination if an external filter is inserted between
IMXO(QMXO) and IAIN(QAIN). The DC output level of
the buffer is set by the VCMO pin. This can be set externally or connected to the on-chip 1.0V reference VREF.
Phase splitter Quadrature generation is achieved using a divide-by-two
frequency divider. Unlike a poly-phase filter which achieves
quadrature over a limited frequency range, the divide-by-two
approach maintains quadrature over a broad frequency range and does not attenuate the LO. The user, however, must
provide an external reference XLO which is twice the
frequency of the desired LO frequency. XLO drives the clock inputs of two flip-flops which divide down the frequency by a
factor of two. The outputs of the two flip-flops are one half-
period of XLO out of phase. Equivalently, the outputs are one
quarter-period (90 degrees) of the desired LO frequency out of
phase. Because the transitions on XLO define the phase difference at the outputs, deviation from 50% duty cycle
translates directly to quadrature phase errors.
Baseband amplifiers Two (I &Q) fixed-gain (20dB), single-ended to differential
amplifers are provided to amplify the demodulated signal after
off-chip filtering. The amplifiers use voltage feedback to linearize the gain over the demolation bandwidth. These
amplifiers can be used to maximize the dynamic range at the
input of an ADC following the AD8348.
The input to the baseband amplifiers IAIN (QAIN) feeds into
the base of a bipolar transistor with an input impedance of roughly 100kohm. The baseband amplifiers sense the single-
ended difference between IAIN (QAIN) and VCMO. IAIN
can be DC biased by terminating with a shunt resistor to
VCMO, such as when an external filter is inserted between IMXO (QMXO) and IAIN (QAIN). Alternatively, any DC
connection to IMXO (QXMO) can provide appropriate bias
via the offset-nulling loop.
Bias The global bias for the chip is controlled by a master biasing
cell that can be disabled using the ENBL pin. If the ENBL is held low, the entire chip will power down to a low-power
sleep mode typically consuming 60uA at 5V.
Baseband offset cancellation A low output current integrator senses the output voltage
offset at IOPP,IOPN (QOPP,QOPN) and injects a nulling current into the signal path. The integration time constant of
the offset nulling loop is set by capacitor COFS from IOFS
(QOFS) to VCMO. This forms a high-pass response for the
baseband signal path with a lower 3dB frequency of 1200pass
OFSfCπ=⋅Ω⋅
Alternatively, the user can externally adjust the DC offset by driving IOFS (QOFS) with a digital-to-analog converter or
other voltage source. In this case, the baseband circuit will
operate all the way down to DC (fpass=0Hz). The integrator output current is only 50uA and can be easily overridden with
an external voltage source. The IOFS (QOFS) pin must be
either connected to a bypass capacitor (>0.1uF) or an external
voltage source to prevent the feedback loop from oscillating.
