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AD8345ARE
250 MHz.1000 MHz Quadrature Modulator
REV. 0
250 MHz–1000 MHz
Quadrature Modulator
FUNCTIONAL BLOCK DIAGRAM
FEATURES
250 MHz–1000 MHz Operating Frequency
+2.5 dBm P1 dB @ 800 MHz
–155 dBm/Hz Noise Floor
0.5 Degree RMS Phase Error (IS95)
0.2 dB Amplitude Balance
Single 2.7 V–5.5 V Supply
Pin-Compatible with AD8346
16-Lead Exposed Paddle TSSOP Package
APPLICATIONS
Cellular Communication Systems
W-CDMA/CDMA/GSM/PCS/ISM Transceivers
Fixed Broadband Access Systems LMDS/MMDS
Wireless LAN
Wireless Local Loop
Digital TV/CATV Modulators
Single Sideband Upconverter
PRODUCT DESCRIPTIONThe AD8345 is a silicon RFIC quadrature modulator, designed
for use from 250 MHz to 1000 MHz. Its excellent phase accu-
racy and amplitude balance enable the high performance direct
modulation of an IF carrier.
The AD8345 accurately splits the external LO signal into two
quadrature components through the polyphase phase-splitter
network. The two I and Q LO components are mixed with the
baseband I and Q differential input signals. Finally, the outputs
of the two mixers are combined in the output stage to provide a
single-ended 50Ω drive at VOUT.
APPLICATIONSThe AD8345 Modulator can be used as the IF transmit modu-
lator in digital communication systems such as GSM and PCS
transceivers. It can also directly modulate an LO signal to
produce QPSK and various QAM formats for 900 MHz com-
munication systems as well as digital TV and CATV systems.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8345 Modulator is supplied in a 16-lead TSSOP pack-
age with exposed paddle. Its performance is specified over a
–40°C to +85°C temperature range. This device is fabricated on
Analog Devices’ advanced silicon bipolar process.
AD8345–SPECIFICATIONS(VS = 5 V; LO= –2 dBm @ 800 MHz, 50 � source and load impedances, I and Q inputs
0.7 V � 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency.
TA = 25�C, unless otherwise noted.)POWER SUPPLIES
NOTESFor information on operation below 250 MHz, see Figure 4.See LO Drive section for more details on input matching.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8345 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power LOIP, LOIN (re 50 Ω) . . . . . . . . . . . . . 10 dBm
IBBP, IBBN, QBBP, QBBN . . . . . . . . . . . . . . . . . 0 V, 2.5 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW
θJA (Exposed Paddle Soldered Down) . . . . . . . . . . . . 30°C/W
θJA (Exposed Paddle not Soldered Down) . . . . . . . . . 95°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
ORDERING GUIDEAD8345ARE-REEL
AD8345ARE-REEL7
AD8345
PIN FUNCTION DESCRIPTIONS15, 16
EQUIVALENT CIRCUITSCircuit A
Circuit B
Circuit C
Circuit D
Figure 1.Equivalent Circuits
TPC 1.Single Sideband (SSB) Output Power (POUT) vs. LO
Frequency (FLO). (I and Q Inputs Driven in Quadrature at
Baseband Frequency (FBB) = 1 MHz; TA = 25°C)
TPC 2.I and Q Input Bandwidth. (TA = 25°C, FLO = 800 MHz,
LO Level = –2 dBm, I and Q Inputs Driven in Quadrature)
TPC 4.SSB Output 1 dB Compression Point (OP 1 dB) vs.
FLO. (VS = 2.7 V, LO Level = –2 dBm, I and Q Inputs Driven
in Quadrature, FBB = 1 MHz)
TPC 5.SSB Output 1 dB Compression Point (OP 1 dB) vs.
FLO. (VS = 5 V, LO Level = –2 dBm, I and Q Inputs Driven in
Quadrature, FBB = 1 MHz)
AD8345TPC 7.Carrier Feedthrough vs. Temperature.
(FLO = 800 MHz, LO Level = –2 dBm)
TPC 8.Carrier Feedthrough Distribution at Temperature
Extremes. After Feedthrough Nulled to <–65 dBm at TA =
25°C. (FLO = 800 MHz, LO Level = –2 dBm)
TPC 9.Sideband Suppression vs. FLO. (TA = 25°C,
TPC 10.Sideband Suppression vs. FBB. (TA = 25°C,
FLO = 800 MHz, LO Level = –2 dBm, I and Q Inputs
Driven in Quadrature)
TPC 11.Sideband Suppression vs. Temperature.
(FLO = 800 MHz, LO Level = –2 dBm, FBB =1 MHz,
I and Q Inputs Driven in Quadrature)
TPC 12.Third Order Distortion vs. FBB. (TA = 25°C,
TPC 13.Third Order Distortion vs. Temperature.
(FLO = 800 MHz, LO Level = –2 dBm, FBB =1 MHz,
I and Q Inputs Driven in Quadrature)
TPC 14.Third Order Distortion and SSB POUT vs. Base-
band Differential Input Level. (TA = 25°C, FLO = 800MHz,
LO Level = –2 dBm, FBB = 1 MHz, VS = 2.7 V)
TPC 16.Power Supply Current vs. Temperature
WITH 50�
WITH 100�
LOIN NO BALUN
OR TERMINATION
SMITH CHART
NORMALIZED
TO 50�TPC 17.Smith Chart of LOIN Port S11 (LOIP Pin AC-
Coupled to Ground). Curves with Balun and External
Termination Resistors Also Shown. (VS = 5 V,
TA = 25°C)
AD8345
CIRCUIT DESCRIPTION
OverviewThe AD8345 can be divided into the following sections: Local
Oscillator (LO) Interface, Mixer, Differential Voltage-to-Cur-
rent (V-to-I) Converter, Differential-to-Single-Ended (D-to-S)
Converter, and Bias. A block diagram of the part is shown in
Figure 2.
Figure 2.AD8345 Block Diagram
The LO Interface generates two LO signals at 90 degrees of
phase difference with each other, to drive two mixers in quadra-
ture. Baseband signals are converted into current form in the
Differential V-to-I Converters, feeding into the two mixers. The
outputs of the mixers are combined to feed the Differential-to-
Single-Ended Converter, which provides a 50 Ω output interface.
Bias currents to each section are controlled by the Enable
(ENBL) signal. Detailed description of each section follows.
LO InterfaceThe LO Interface consists of interleaved stages of polyphase
phase-splitters and buffer amplifiers. The polyphase phase-splitter
contains resistors and capacitors connected in a circular manner
to split the LO signal into I and Q paths in precise quadra-
ture with each other. The signal on each path goes through a
buffer amplifier to make up for the loss and high frequency
roll-off. The two signals then go through another polyphase
network to enhance the quadrature accuracy. The broad oper-
ating frequency range (250 MHz to 1000 MHz) is achieved
by staggering the RC time constants of each stage of the phase-
splitters. The outputs of the second phase-splitter are fed into
the driver amplifiers for the mixers’ LO inputs.
Differential V-to-I ConverterIn this circuit, each baseband input pin is connected to an op amp
driving a transistor connected as an emitter follower. A resistor
between the two emitters maintains a varying current propor-
tional to the differential input voltage through the transistor. These
currents are fed to the two mixers in differential form.
MixersThere are two double-balanced mixers, one for the In-phase
Channel (I-Channel) and one for the Quadrature Channel (Q-
Channel). Each mixer uses the Gilbert-cell design with four
cross-connected transistors. The bases of the transistors are
driven by the LO signal of the corresponding channel. The
output currents from the two mixers are summed together in
two load resistors. The signal developed across the load resistors
is sent to the D-to-S stage.
Differential to Single-Ended ConverterThe differential-to-single-ended converter consists of two emit-
ter followers driving a totem-pole output stage whose output
impedance is established by the emitter resistors in the output
transistors. The output of this stage is connected to the output
(VOUT) pin.
BiasA bandgap reference circuit based on the ∆-VBE principle gen-
erates the Proportional-To-Absolute-Temperature (PTAT) as
well as temperature-stable currents used by the different sec-
tions as references. When the bandgap reference is disabled by
pulling down the voltage at the ENBL pin, all other sections are
shut off accordingly.
TPC 19.Noise Floor vs. LO Input Power. (TA = 25°C, FLO =
800 MHz, VS = 5 V, All I and Q Inputs are DC-Biased to
0.7V) Noise Measured at 20 MHz Offset from Carrier
TPC 20.LO Feedthrough vs. LO Input Power. (TA = 25°C,
LO = 800 MHz, VS = 5.5 V)
