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AD8343ARU-AD8343ARU-REEL7
DC-to-2.5 GHz High IP3 Active Mixer
REV.0
DC-to-2.5 GHz
High IP3 Active Mixer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High-Performance Active Mixer
Broadband Operation to 2.5 GHz
Conversion Gain: 7.1 dB
Input IP3: 16.5 dBm
LO Drive: –10 dBm
Noise Figure: 14.1 dB
Input P1dB: 2.8 dBm
Differential LO, IF and RF Ports� LO Input Impedance
Single-Supply Operation: 5 V @ 50 mA Typical
Power-Down Mode @ 20 �A Typical
APPLICATIONS
Cellular Base Stations
Wireless LAN
Satellite Converters
SONET/SDH Radio
Radio Links
RF Instrumentation
PRODUCT DESCRIPTIONThe AD8343 is a high-performance broadband active mixer.
Having wide bandwidth on all ports and very low intermodulation
distortion, the AD8343 is well suited for demanding transmit or
receive channel applications.
The AD8343 provides a typical conversion gain of 7.1 dB. The
integrated LO driver supports a 50Ω differential input imped-
ance with low LO drive level, helping to minimize external
component count.
The open-emitter differential inputs may be interfaced directly
to a differential filter or driven through a balun (transformer) to
provide a balanced drive from a single-ended source.
The open-collector differential outputs may be used to drive a
differential IF signal interface or converted to a single-ended
signal through the use of a matching network or transformer.
When centered on the VPOS supply voltage, the outputs may
swing ±1 V.
The LO driver circuitry typically consumes 15mA of current.
Two external resistors are used to set the mixer core current for
required performance resulting in a total current of 20mA tomA. This corresponds to power consumption of 100 mW to
300 mW with a single 5 V supply.
The AD8343 is fabricated on Analog Devices’ proprietary, high-
performance 25 GHz silicon bipolar IC process. The AD8343 is
available in a 14-lead TSSOP package. It operates over a –40°C
to +85°C temperature range. A device-populated evaluation
board is available to facilitate device matching.
AD8343–SPECIFICATIONS
BASIC OPERATING CONDITIONSOUTPUT INTERFACE (OUTP, OUTM)
LO INTERFACE (LOIP, LOIM)
POWER-DOWN INTERFACE (PWDN)
NOTESThe balance in the bias current in the two legs of the mixer input may be important in applications were a low feedthrough of the LO is critical.This voltage is proportional to absolute temperature (PTAT). Reference section on DC-Coupling the LO for more information regarding this interface.Response time until device meets all specified conditions.
Specifications subject to change without notice.
(VS = 5.0 V, TA = 25�C)
Table I.Typical AC Performance
(VS = 5.0 V, TA = 25�C; See Figure 24 and Tables III Through V.)TRANSMITTER CHARACTERISTICS
Table II.Typical Isolation Performance
(VS = 5.0 V, TA = 25�C; See Figure 24 and Tables III Through V.)TRANSMITTER CHARACTERISTICS
NOTE: Low-side LO injection used for typical performance.
ABSOLUTE MAXIMUM RATINGS1VPOS Quiescent Voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
OUTP, OUTM Quiescent Voltage . . . . . . . . . . . . . . . . 5.5 V
INPP, INPM Voltage Differential . . . . . . . . . . . . . . . 500 mV
Internal Power Dissipation (TSSOP)2 . . . . . . . . . . . . 320 mW
θJA (TSSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.A portion of the device power is dissipated by the external bias resistors R3 and R4.
ORDERING GUIDE
PIN CONFIGURATION
AD8343
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8343 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS1, 7, 8,
CONVERSION GAIN – dB
PERCENTAGE
5.425.475.525.575.625.675.72TPC 1.Gain Histogram fIN = 400 MHz, fOUT = 70 MHz
TPC 2.Input IP3 Histogram fIN = 400 MHz, fOUT = 70 MHz
TPC 4.Gain Performance Over Temperature
fIN = 400 MHz, fOUT = 70 MHz
TPC 5.Input IP3 Performance Over Temperature
fIN = 400MHz, fOUT = 70 MHz
RECEIVER CHARACTERISTICS(fIN = 400 MHz, fOUT = 70MHz, fLO = 330 MHz [Figure 24, Tables III and IV])
AD8343
CONVERSION GAIN – dB
PERCENTAGE
3.403.503.553.603.653.703.753.803.85TPC 7.Gain Histogram fIN = 900 MHz, fOUT = 170 MHz
INPUT IP3 – dBm
PERCENTAGE
18.418.618.819.019.219.419.619.820.020.2TPC 8.Input IP3 Histogram fIN = 900 MHz, fOUT = 170 MHz
INPUT 1dB COMPRESSION POINT – dBm3.52
PERCENTAGE
RECEIVER CHARACTERISTICS(fIN = 900 MHz, fOUT = 170MHz, fLO = 730 MHz [Figure 24, Tables III and IV])TPC 10.Gain Performance Over Temperature
fIN = 900MHz, fOUT = 170 MHz
TPC 11.Input IP3 Performance Over Temperature
fIN = 900MHz, fOUT = 170 MHz
CONVERSION GAIN – dB
PERCENTAGE
6.906.857.006.957.107.057.207.157.307.25TPC 13.Gain Histogram fIN = 1900 MHz, fOUT = 170 MHz
INPUT IP3 – dBm
PERCENTAGE
14.515.015.516.016.517.017.518.0TPC 14.Input IP3 Histogram fIN = 1900 MHz,
fOUT = 170MHz
INPUT 1dB COMPRESSION POINT – dBm2.60
PERCENTAGE
2.652.702.752.802.852.902.953.003.05TPC 16.Gain Performance Over Temperature
fIN = 1900MHz, fOUT = 170 MHz
TPC 17.Input IP3 Performance Over Temperature
fIN = 1900 MHz, fOUT = 170 MHz
RECEIVER CHARACTERISTICS(fIN = 1900 MHz, fOUT = 170 MHz, fLO = 1730 MHz [Figure 24, Tables III and IV])
AD8343
CONVERSION GAIN – dB
PERCENTAGE
5.86.26.46.66.87.07.27.47.6TPC 19.Gain Histogram fIN = 2400 MHz, fOUT = 170 MHz
INPUT IP3 – dBm
PERCENTAGE
13.213.413.613.814.014.214.414.614.815.015.215.415.6TPC 20.Input IP3 Histogram fIN = 2400 MHz, fOUT = 170MHz
INPUT 1dB COMPRESSION POINT – dBm
PERCENTAGE
1.952.002.052.102.152.202.252.302.352.40TPC 22.Gain Performance Over Temperature
fIN = 2400MHz, fOUT = 170 MHz
TPC 23.Input IP3 Performance Over Temperature
fIN = 2400MHz, fOUT = 170 MHz
RECEIVER CHARACTERISTICS(fIN = 2400 MHz, fOUT = 170MHz, fLO = 2230 MHz [Figure 24, Tables III and IV])
CONVERSION GAIN – dB
PERCENTAGE
6.26.4TPC 25.Gain Histogram fIN = 2400 MHz, fOUT = 425 MHz
INPUT IP3 – dBm
PERCENTAGE
17.018.015.215.0TPC 26.Input IP3 Histogram fIN = 2400 MHz,
fOUT = 425 MHz
INPUT 1dB COMPRESSION POINT – dBm
PERCENTAGE
RECEIVER CHARACTERISTICS(fIN = 2400 MHz, fOUT = 425MHz, fLO = 1975 MHz [Figure 24, Tables III and IV])TPC 28.Gain Performance Over Temperature
fIN = 2400MHz, fOUT = 425 MHz
TPC 29.Input IP3 Performance Over Temperature
fIN = 2400MHz, fOUT = 425 MHz
AD8343
TRANSMIT CHARACTERISTICS(fIN = 150 MHz, fOUT = 900MHz, fLO = 750 MHz [Figure 24, Tables III and IV])
CONVERSION GAIN – dB
PERCENTAGE
7.257.307.357.407.457.507.557.607.65TPC 31.Gain Histogram fIN = 150 MHz, fOUT = 900 MHz
INPUT IP3 – dBm
PERCENTAGE
17.917.9518.018.0518.118.1518.218.2518.318.3518.418.45TPC 32.Input IP3 Histogram fIN = 150 MHz, fOUT = 900 MHz
TPC 34.Gain Performance Over Temperature
fIN = 150MHz, fOUT = 900 MHz
TPC 35.Input IP3 Performance Over Temperature
fIN = 150MHz, fOUT = 900 MHz
TRANSMIT CHARACTERISTICS(fIN = 150 MHz, fOUT = 1900MHz, fLO = 1750 MHz [Figure 24, Tables III and IV])
CONVERSION GAIN – dB
PERCENTAGE
–0.6–0.4–0.200.20.40.60.81.01.21.4TPC 37.Gain Histogram fIN = 150 MHz, fOUT = 1900 MHz
INPUT IP3 – dBm
PERCENTAGE
11.011.512.012.513.013.514.014.515.015.516.016.517.0TPC 38.Input IP3 Histogram fIN = 150 MHz,
fOUT = 1900MHz
INPUT 1dB COMPRESSION POINT – dBm–1–0.5
PERCENTAGE0.51.01.52.02.53.03.5TPC 40.Gain Performance Over Temperature
fIN = 150MHz, fOUT = 1900 MHz
TPC 41.Input IP3 Performance Over Temperature
fIN = 150MHz, fOUT = 1900 MHz
AD8343
CIRCUIT DESCRIPTIONThe AD8343 is a mixer intended for high-intercept applications.
The signal paths are entirely differential and dc-coupled to permit
high-performance operation over a broad range of frequencies;
the block diagram (Figure 1) shows the basic functional blocks.
The bias cell provides a PTAT (proportional to absolute tem-
perature) bias to the LO Driver and Core. The LO Driver
consists of a three-stage limiting differential amplifier that pro-
vides a very fast (almost square-wave) drive to the bases of the
core transistors.
The AD8343 core utilizes a standard architecture in which the
signal inputs are directly applied to the emitters of the transistors in
the cell (Figure 7). The bases are driven by the hard-limited LO
signal that directs the transistors to steer the input currents into
periodically alternating pairs of output terminals, thus providing
the periodic polarity reversal that effectively multiplies the signal
by a square wave of the LO frequency.
BIAS
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPPINPM
OUTP
OUTM
COMM
MIXER
CORE
DRIVERQ2Q3Q4Figure 1.Topology
To illustrate this functionality, when LOIP is positive, Q1 and
Q4 are turned ON, and Q2 and Q3 are turned OFF. In this
condition Q1 connects IINPP to OUTM and Q4 connects IINPM
to OUTP. When LOIP is negative the roles of the transistors
reverse, steering IINPP to OUTP and IINPM to OUTM. Isolation
and gain are possible because at any instant the signal passes
through a common-base transistor amplifier pair.
Multiplication is the essence of frequency mixing; an ideal multi-
plier would make an excellent mixer. The theory is expressed in
the following trigonometric identity:
sin(ωsigt)sin(ωLOt) = 1/2 [cos(ωsigt – ωLOt) – cos(ωsigt + ωLOt)]
This states that the product of two sine-wave signals of different
frequencies is a pair of sine waves at frequencies equal to the
sum and difference of the two frequencies being multiplied.
Unfortunately, practical implementations of analog multipliers
generally make poor mixers because of imperfect linearity and
because of the added noise that invariably accompanies attempts
to improve linearity. The best mixers to date have proven to be
those that use the LO signal to periodically reverse the polarity
of the input signal.
In this class of mixers, frequency conversion occurs as a result
of multiplication of the signal by a square wave at the LO
frequency. Because a square wave contains odd harmonics in
addition to the fundamental, the signal is effectively multiplied
by each frequency component of the LO. The output of the
mixer will therefore contain signals at FLO ± Fsig, 3 × FLO ± Fsig,
5 × FLO ± Fsig, 7 × FLO ± Fsig, etc. The amplitude of the compo-
nents arising from signal multiplication by LO harmonics falls
off with increasing harmonic order because the amplitude of a
square wave’s harmonics falls off.
An example of this process is illustrated in Figure 2. The first
pane of this figure shows an 800 MHz sinusoid intended to
represent an input signal. The second pane contains a square
wave representing an LO signal at 600 MHz which has been
hard-limited by the internal LO driver. The third pane shows
the time domain representation of the output waveform and the
fourth pane shows the frequency domain representation. The
two strongest lines in the spectrum are the sum and difference
frequencies arising from multiplication of the signal by the LO’s
fundamental frequency. The weaker spectral lines are the result
of the multiplication of the signal by various harmonics of the
LO square wave.
Figure 2.Signal Switching Characteristics of the AD8343
DC INTERFACES
Biasing and Decoupling (VPOS, DCPL)VPOS is the power supply connection for the internal bias cir-
cuit and the LO driver. This pin should be closely bypassed to
GND with a capacitor in the range of 0.01µF to 0.1 µF. The
DCPL pin provides access to an internal bias node for noise
bypassing purposes. This node should be bypassed to COMM
with 0.1 µF.
Power-Down Interface (PWDN)The AD8343 is active when the PWDN pin is held low; other-
wise the device enters a low-power state as shown in Figure 3.
Figure 3.Bias Current vs. PWDN Voltage
To assure full power-down, the PWDN voltage should be within
0.5V of the supply voltage at VPOS. Normal operation requires
that the PWDN pin be taken at least 1.5 V below the supply
voltage. The PWDN pin sources about 100 µA when pulled to
GND (refer to Pin Function Descriptions). It is not advisable to
leave the pin floating when the device is to be disabled; a resis-
tive pull-up to VPOS is the minimum suggestion.
The AD8343 requires about 2.5 µs to turn OFF when PWDN is
asserted; turn ON time is about 500 ns. Figures 4 and 5 show
typical characteristics (they will vary with bypass component
values). Figure 6 shows the test configuration used to acquire
these waveforms.
Figure 4.PWDN Response Time Device ON to OFF
Figure 5.PWDN Response Time Device OFF to ON
Figure 6.PWDN Response Time Test Schematic
AC INTERFACESBecause of the AD8343’s wideband design, there are several
points to consider in its ac implementation; the Basic AC
Signal Connection diagram shown in Figure 7 summarizes
these points. The input signal undergoes a single-ended-to-
differential conversion and is then reactively matched to the
impedance presented by the emitters of the core. The matching
network also provides bias currents to these emitters. Similarly,
the LO input undergoes a single-ended-to-differential transfor-
mation before it is applied to the 50 Ω differential LO port. The
differential output signal currents appear at high-impedance
collectors and may be reactively matched and converted to a
single-ended signal.
AD8343Figure 7.Basic AC Signal Connection Diagram
INPUT INTERFACE (INPP AND INPM)
Single-Ended-to-Differential ConversionThe AD8343 is designed to accept differential input signals for
best performance. While a single-ended input can be applied,
the signal capacity is reduced by 6 dB. Further, there would be
no cancellation of even-order distortion arising from the nonlin-
ear input impedances, so the effective signal handling capacity
will be reduced even further in distortion-sensitive situations.
That is, the intermodulation intercepts are degraded.
For these reasons it is strongly recommended that differential
signals be presented to the AD8343’s input. In addition to com-
mercially available baluns, there are various discrete and printed
circuit elements that can produce the required balanced wave-
forms and impedance match (i.e., rat-race baluns). These
alternate circuits can be employed to further reduce the compo-
nent cost of the mixer.
Baluns implemented in transmission line form (also known as
common-mode chokes) are useful up to frequencies of aroundGHz, but are often excessively lossy at the highest frequencies
that the AD8343 can handle. M/A-Com manufactures these
baluns with their ETC line. Murata produces a true surface-
mount balun with their LDB20C series. Coilcraft and Toko are
also manufacturers of RF baluns.
Input Matching ConsiderationsThe design of the input matching network should be undertaken
with two goals in mind: matching the source impedance to the
input impedance of the AD8343 and providing a dc bias current
The maximum power transfer into the device will occur when
there is a conjugate impedance match between the signal source
and the input of the AD8343. This match can be achieved with
the differential equivalent of the classic “L” network, as illustrated
in Figure 8. The figure gives two examples of the transformation
from a single-ended “L” network to its differential counterpart.
The design of “L” matching networks is adequately covered in
texts on RF amplifier design (for example: “Microwave Transis-
tor Amplifiers” by Guillermo Gonzalez).
Figure 8.Single-Ended-to-Differential Transformation
Figure 9 shows the differential input impedance of the AD8343
at the pins of the device. The two measurements shown in the
figure are for two different core currents set by resistors R3 and
R4; the real value impedance shift is caused by the change in tran-
sistor rE due to the change in current. The standard S parameter
files are available at the ADI web site ().
Figure 9.Input Differential Impedance (INPP, INPM) for
Two Values of R3 and R4
Figure 9 provides a reasonable starting point for the design of
the network. However, the particular board traces and pads will
transform the input impedance at frequencies in excess of about
500 MHz. For this reason it is best to make a differential input
impedance measurement at the board location where the match-
ing network will be installed, as a starting point for designing an
accurate matching network.
Differential impedance measurement is made relatively easy
through the use of a technique presented in an article by Lutz
Konstroffer in RF Design, January 1999, entitled “Finding the
Reflection Coefficient of a Differential One-Port Device.” This
article presents a mathematical formula for converting from a
two-port single-ended measurement to differential impedance.
A full two-port measurement is performed using a vector network
analyzer with Port 1 and Port 2 connected to the two differential
inputs of the device at the desired measurement plane. The two-
port measurement results are then processed with Konstroffer’s
