AD8328ARQ-REEL ,5 V Upstream Cable Line Driverspecifications. Typical insertion loss of 0.3 dB @ 10 MHz.2Guaranteed by design and characterizatio ..
AD8328ARQ-REEL ,5 V Upstream Cable Line Driverspecifications make the AD8328 –54@MAX GAIN,ideally suited for MCNS-DOCSIS and Euro-DOCSIS applica- ..
AD8330ARQ ,Low Cost DC-150 MHz Variable Gain AmplifierSPECIFICATIONS V = 0/C, V = 0 V, Differential Operation, unless otherwise noted.)MAG OFSTParameter ..
AD8330ARQZ , Low Cost, DC to 150 MHz Variable Gain Amplifier
AD8330ARQZ , Low Cost, DC to 150 MHz Variable Gain Amplifier
AD8330ARQZ-R7 , Low Cost, DC to 150 MHz Variable Gain Amplifier
ADP3300ARTZ-2.7RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorSpecifications subject to change without notice.–2– REV. BADP3300ABSOLUTE MAXIMUM RATINGS* PIN FUNC ..
ADP3300ARTZ-2.7-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorGENERAL DESCRIPTION +R1C1C2330kThe ADP3300 is a member of the ADP330x family of precision 0.47F0. ..
ADP3300ARTZ-3.3RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorGENERAL DESCRIPTION +R1C1C2330kThe ADP3300 is a member of the ADP330x family of precision 0.47F0. ..
ADP3300ARTZ-3.3-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear Regulatorfeatures include shutdown andture, line and load variations. The dropout voltage of theoptional noi ..
ADP3300ARTZ-3-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorFEATURES FUNCTIONAL BLOCK DIAGRAMHigh Accuracy Over Line and Load: 0.8% @ 25C,1.4% Over Temperat ..
ADP3300ARTZ-5REEL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorAPPLICATIONSCellular TelephonesNotebook, Palmtop ComputersBattery Powered SystemsPCMCIA RegulatorsB ..
AD8328ARQ-AD8328ARQ-REEL
5 V Upstream Cable Line Driver
REV. 0
5 V Upstream
Cable Line Driver
FEATURES
Supports DOCSIS and EuroDOCSIS Standards for
Reverse Path Transmission Systems
Gain Programmable in 1 dB Steps over a 59 dB Range
Low Distortion at 60dBmV Output:
–57.5 dBc SFDR at 21MHz
–54 dBc SFDR at 65MHz
Output Noise Level @ Minimum Gain 1.2nV/√Hz
Maintains 300 � Output Impedance TX-Enable and
Transmit-Disable Condition
Upper Bandwidth: 107 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces
APPLICATIONS
DOCSIS and EuroDOCSIS Cable Modems
CATV Set-Top Boxes
CATV Telephony Modems
Coaxial and Twisted Pair Line Driver
GENERAL DESCRIPTIONThe AD8328 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8328
ideally suited for MCNS-DOCSIS and Euro-DOCSIS applica-
tions. The gain of the AD8328 is digitally controlled. An 8-bit
serial word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8328 accepts a differential or single-ended input signal. The
output is specified for driving a 75 Ω load through a 2:1transformer.
Distortion performance of –53 dBc is achieved with an output
level up to 60dBmV at 65MHz bandwidth over a wide tempera-
ture range.
This device has a sleep mode function that reduces the quiescent
current to 2.6 mA and a full power-down function that reduces
power-down current to 20 µA.
The AD8328 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8328 operates from a single
5V supply and has an operational temperature range of –40°C+85°C.
FUNCTIONAL BLOCK DIAGRAM
DATENSDATACLKTXENSLEEP
VOUT+
VOUT–
VIN+
VIN–
BYP
GND
RAMPFigure 1.Worst Harmonic Distortion vs. Frequency
*Patent Pending
AD8328–SPECIFICATIONSOUTPUT CHARACTERISTICS
OPERATING TEMPERATURE
NOTESTOKO 458PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz.Guaranteed by design and characterization to ±4 sigma for TA = 25°C.Measured through a 2:1 transformer.Specification is worst case over all gain codes.Guaranteed by design and characterization to ±3 sigma for TA = 25°C.
(TA = 25�C, VS = 5 V, RL = RIN = 75 �, VIN (Differential) = 29 dBmV.
The AD8328 is characterized using a2:1 transformer1 at the device output.)
AD8328
LOGIC INPUTS (TTL/CMOS Compatible Logic)Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN
Logic 0 Current (VINL = 0 V) TXEN
Logic 1 Current (VINH = 5 V) SLEEP
Specifications subject to change without notice.
TIMING REQUIREMENTSSpecifications subject to change without notice.
Figure 2.Serial Interface Timing
(Full Temperature Range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.)
(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V. Full Temperature Range.)
AD8328
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V
Input Voltage
VIN+, VIN– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V p-p
DATEN, SDATA, CLK,
SLEEP, TXEN . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
QSOP, LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . .700 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN CONFIGURATIONS
ORDERING GUIDEThermal Resistance measured on SEMI standard 4-layer board.Thermal Resistance measured on SEMI standard 4-layer board, paddle soldered to board.
20-Lead
QSOP
20-Lead
LFCSP
PIN FUNCTION DESCRIPTIONS810CLK
TPC 1.Second-Order Harmonic Distortion
vs. Frequency for Various Output Powers
TPC 2.Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
TPC 3.Adjacent Channel Power
TPC 4.Third-Order Harmonic Distortion vs.
Frequency for Various Output Powers
TPC 5.Third-Order Harmonic Distortion vs.
Frequency vs. Temperature
TPC 6.Two-Tone Intermodulation Distortion
AD8328 TPC 7.AC Response
TPC 8.Output Step Size vs. Gain Control
TPC 9.Output Referred Voltage Noise vs. Gain Control
TPC 10.Isolation in Transmit Disable
Mode vs. Frequency
TPC 11.Gain Error vs. Gain Control
TPC 12.Supply Current vs. Gain Control
Figure 4.Characterization Circuit
APPLICATIONS
General ApplicationsThe AD8328 is primarily intended for use as the power amplifier
(PA) in DOCSIS (Data Over Cable Service Interface Specification)
certified cable modems and CATV set-top boxes. The upstream
signal is either a QPSK or QAM signal generated by a DSP, a
dedicated QPSK/QAM modulator, or a DAC. In all cases, the
signal must be low-pass filtered before being applied to the PA in
order to filter out-of-band noise and higher order harmonics from
the amplified signal.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the output
power by applying gain or attenuation. The ability to vary the
output power of the AD8328 ensures that the signal from the cable
modem will have the proper level once it arrives at the head-end.
The upstream signal path commonly includes a diplexer and cable
splitters. The AD8328 has been designed to overcome losses asso-
ciated with these passive components in the upstream cable path.
Circuit DescriptionThe AD8328 is composed of three analog functions in the power-up
or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differential
configuration, it is imperative that the input signals be 180degrees out
of phase and of equal amplitude. A vernier is used in the input
stage for controlling the fine 1dB gain steps. This stage then drives
a DAC, which provides the bulk of the AD8328’s attenuation. The
signals in the preamp and DAC gain blocks are differential to
improve the PSRR and linearity. A differential current is fed from
the DAC into the output stage. The output stage maintains 300Ω
differential output impedance, which maintains proper match to 75 Ω
when used with a 2:1 balun transformer.
SPI Programming and Gain AdjustmentThe AD8328 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK, DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates the
CLK line. With the CLK line activated, data on the SDATA line
is clocked into the serial shift register on the rising edge of the
CLK pulses, most significant bit (MSB) first. The 8-bit data-word
is latched into the attenuator core on the rising edge of the
DATEN line. This provides control over the changes in the
output signal level. The serial interface timing for the AD8328
is shown in Figures 2 and 3. The programmable gain range of
the AD8328 is –28 dB to +31 dB with steps of 1 dB per least
significant bit (LSB). This provides a total gain range of 59 dB.
The AD8328 was characterized with a differential signal on the
input and a TOKO 458PT-1087 2:1 transformer on the output.
The AD8328 incorporates supply current scaling with gain code,
as seen in TPC 12. This allows reduced power consumption when
operating in lower gain codes.
Input Bias, Impedance, and TerminationThe VIN+ and VIN– inputs have a dc bias level of VCC/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (see Figure 5). The differential input impedance
of the AD8328 is approximately 1.6 kΩ, while the single-ended
input is 800 Ω. The high input impedance of the AD8328 allows
flexibility in termination and properly matching filter networks.
The AD8328 will exhibit optimum performance when driven
with a pure differential signal.
Output Bias, Impedance, and TerminationThe output stage of the AD8328 requires a bias of +5 V. The
+5 V power supply should be connected to the center tap of the
output transformer. Also, the VCC that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical applications circuit (Figure 5).
AD8328The output impedance of the AD8328 is 300 Ω, regardless of
whether the amplifier is in transmit enable or transmit disable
mode. This, when combined with a 2:1 voltage ratio (4:1 imped-
ance ratio) transformer, eliminates the need for external back
termination resistors. If the output signal is being evaluated
using standard 50 Ω test equipment, a minimum loss 75 Ω–50 Ω
pad must be used to provide the test circuit with the proper
impedance match. The AD8328 evaluation board provides a
convenient means to implement a matching attenuator. Soldering
a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in
the R16 placeholder will allow testing on a 50 Ω system. When
using a matching attenuator, it should be noted that there will
be a 5.7 dB of power loss (7.5 dB voltage) through the network.
Power SupplyThe 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 �F tantalum capacitor located close to the AD8328. In
addition to the 10 �F capacitor, each VCC pin should be indi-
vidually decoupled to ground with ceramic chip capacitors
located close to the pins. The bypass pin, labeled BYP, should
also be decoupled. The PCB should have a low impedance
ground plane covering all unused portions of the board, except
in areas of the board where input and output traces are in close
proximity to the AD8328 and the output transformer. All AD8328
ground pins must be connected to the ground plane to ensure
proper grounding of all internal nodes.
Signal Integrity Layout ConsiderationsCareful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short will minimize parasitic capacitance and inductance. This
is most critical between the outputs of the AD8328 and the 2:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the input
and output traces should be adequately spaced to minimize
coupling (crosstalk) through the board. Following these guide-
lines will optimize the overall performance of the AD8328 in all
applications.
Initial Power-UpWhen the supply voltage is first applied to the AD8328, the gain
of the amplifier is initially set to gain code 1. As power is first
applied to the amplifier, the TXEN pin should be held low
and Gain Adjustment section. The TXEN pin can then be brought
from Logic 0 to Logic 1, enabling forward signal transmission at
the desired gain level.
RAMP Pin and BYP Pin FeaturesThe RAMP pin (Pin 15) is used to control the length of the burst
on and off transients. By default, leaving the RAMP pin unconnected
will result in a transient that is fully compliant with DOCSIS 2.0
Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients.
DOCSIS requires that all between burst transients must be dissi-
pated no faster than 2µs. Adding capacitance to the RAMP pin
will add more time to the transient.
The BYP pin is used to decouple the output stage at midsupply.
Typically, for normal DOCSIS operation, the BYP pin shoulddecoupled to ground with a 0.1 µF capacitor. However, in
applications that may require transient on/off times faster thanµs, smaller capacitors may be used, but it should be noted that
the BYPpin should always be decoupled to ground.
Transmit Enable (TXEN) and SLEEPThe asynchronous TXEN pin is used to place the AD8328 into
between-burst mode. In this reduced current state, the output
impedance of 75 Ω is maintained. Applying Logic 0 to the TXEN
pin deactivates the on-chip amplifier, providing a 97.8% reduction
in consumed power. For 5 V operation, the supply current is
typically reduced from 120 mA to 2.6mA. In this mode of opera-
tion, between-burst noise is minimized and high input to
output isolation is achieved. In addition to the TXEN pin, the
AD8328 also incorporates an asynchronous SLEEP pin, which
may be used to further reduce the supply current to approximatelyµA. Applying Logic 0 to the SLEEP pin places the amplifier into
SLEEP mode. Transitioning into or out of SLEEP mode may
result in a transient voltage at the output of the amplifier.
Distortion, Adjacent Channel Power, and DOCSISTo deliver the DOCSIS required 58dBmV of QPSK signal anddBmV of 16QAM signal, the PA is required to deliver up todBmV. This added power is required to compensate for losses
associated with the diplex filter or other passive components that
may be included in the upstream path of cable modems or set-top
boxes. It should be noted that the AD8328 was characterized with
a differential input signal. TPCs 1 and 4 show the AD8328 second
and third harmonic distortion performance versus the fundamental
frequency for various output power levels. These figures are
useful for determining the in-band harmonic levels from 5MHz
to 65MHz. Harmonics higher in frequency (above 42MHz for
Table I.Adjacent Channel Power
Adjacent Channel Symbol Rate (kSym/s)
