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AD8326ARE
High Output Power Programmable CATV Line Driver
REV.0
High Output Power
Programmable CATV Line Driver
FUNCTIONAL BLOCK DIAGRAM
DATENDATACLKVEE (10 PINS)TXENSLEEP
VOUT+
VOUT–
VCC (7 PINS)
VIN+
VIN–
BYP
GND
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 0.75 dB Steps over a 53.5 dB Range
Low Distortion at 65 dBmV Output
–62 dBc SFDR at 21 MHz
–58 dBc SFDR at 65 MHz
1 dB Compression of 25 dBm at 10 MHz
Output Noise Level
–45 dBmV in 160 kHz
Maintains 75 � Output Impedance
Power-Up and Power-Down Condition
Upper Bandwidth: 100 MHz (Full Gain Range)
Single or Dual Supply Operation
APPLICATIONS
Gain-Programmable Line Driver
CATV Telephony Modems
CATV Terminal Devices
General-Purpose Digitally Controlled Variable Gain BlockFigure 1.Worst Harmonic Distortion vs. Frequency
GENERAL DESCRIPTIONThe AD8326 is a high-output power, digitally controlled, vari-
able gain amplifier optimized for coaxial line driving applications
such as data and telephony cable modems that are designed to
the MCNS-DOCSIS upstream standard. An 8-bit serial word
determines the desired output gain over a 53.5 dB range result-
ing in gain changes of 0.75 dB/LSB. The AD8326 is offered in
two models, each optimized to support the desired output power
and resulting performance.
The AD8326 comprises a digitally controlled variable attenuator
of 0 dB to –54 dB, that is preceded by a low noise, fixed-gain
buffer and is followed by a low distortion high-power amplifier.
The AD8326 accepts a differential or single-ended input signal.
The output is designed to drive a 75 Ω load, such as coaxial
cable, although the AD8326 is capable of driving other loads.
When driving 67 dBm into a 75 Ω load, the AD8326ARP
provides a worst harmonic of only –59 dBc at 21 MHz and
–57 dBc at 42 MHz. When driving 65 dBmV into a 75 Ω load,
the AD8326ARE provides a worst harmonic of only –62 dBc at
21 MHz and –60 dBc at 42 MHz.
The differential output of the AD8326 is compliant with DOCSIS
paragraph 4.2.10.2 for “Spurious Emissions During Burst On/Off
Transients.” In addition, this device has a sleep mode function
that reduces the quiescent current to 4mA.
The AD8326 is packaged in a low-cost 28-lead TSSOP and a
28-lead P (power) SOIC. Both devices have an operational tem-
perature range of –40°C to +85°C.
AD8326–SPECIFICATIONS
(TA = 25�C, VS = 12 V, RL = RIN = 75 �, VIN = 259 mV p-p, VOUT measured through a 1:1
transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.)POWER CONTROL
POWER SUPPLY
OPERATING TEMPERATURE
NOTES
1Between Burst Transients measured at the output of diplexer.
Specifications subject to change without notice.
(TA = 25�C, VS = �5 V, RL = RIN = 75 �, VIN = 206 V p-p, VOUT measured through a 1:1
transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.)SPECIFICATIONS
AD8326
LOGIC INPUTS (TTL/CMOS Compatible Logic)Specifications subject to change without notice.
TIMING REQUIREMENTSSpecifications subject to change without notice.
Figure 2.Serial Interface Timing
(Full Temperature Range, VCC = 12 V, tR = tF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 12 V: Full Temperature Range)
ORDERING GUIDE*Thermal Resistance measured on SEMI standard 4-layer board.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VCC
Pins 5, 9, 10, 19, 20, 23, 27 .For ARP, Max VCC = VEE + 13 V;
. . . . . . . . . . . . . . . . . . . . . . .For ARE, Max VCC = VEE + 11 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP EPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W
PSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8326 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD8326
PIN FUNCTION DESCRIPTIONS8, 12, 17
11, 13, 16, 18,
PIN CONFIGURATION
TPC 2.Gain Error vs. Gain Control
TPC 3.AC Response
TPC 1.Test Circuit
TPC 4.AC Response for Various Capacitor Loads
TPC 5.Output Referred Noise vs. Gain Control
AD8326TPC 6.Harmonic Distortion vs. Gain Code for
AD8326-ARP
TPC 7.Second Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 8.Third Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 9.Adjacent Channel Power for AD8326-ARP
TPC 10.Input Impedance vs. Frequency (Inputs
Shunted with 165 Ω)
TPC 11.Output Impedance vs. Frequency
TPC 12.Harmonic Distortion vs. Gain Control for
AD8326-ARE
TPC 13.Second Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 14.Third Order Harmonic Distortion vs. Frequency
for Various Output Powers
TPC 15.Adjacent Channel Power for AD8326-ARE
TPC 16.Signal Isolation vs. Frequency
TPC 17.Quiescent Current vs. Temperature
AD8326
APPLICATIONS
General ApplicationsThe AD8326 is primarily intended for use as the upstream
power amplifier (PA), also known as a line driver, in DOCSIS
(Data Over Cable Service Interface Specification) certified
cable modems, cable telephony systems, and CATV set-top
boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal. Due to the
varying distances between the cable modem and the headend,
the upstream PA must be capable of varying the output power
by applying gain or attenuation. The varying output power of
the AD8326 ensures that the signal from the cable modem will
have the proper level once it arrives at the headend. The upstream
signal path also contains a transformer, a diplexer, and cable split-
ters. The AD8326 has been designed to overcome losses associated
with these passive components in the upstream cable path, particu-
larly in modems that support cable telephony.
AD8326ARP ApplicationsThe AD8326ARP is in a thermally enhanced PSOP2 package,
and designed for single 12 V supply and output power applica-
tions up to +69 dBmV. The AD8326ARP will provide maximum
performance in 12 V systems.
AD8326ARE ApplicationsThe AD8326ARE is in a TSSOP package with an exposed ther-
mal pad. It is designed for dual ±5 V or single 10 V supplies. For
applications requiring up to 65 dBmV of output power, lower
cost, smaller package, and lower power dissipation, the TSSOP
package is most appropriate.
Operational DescriptionThe AD8326 consists of four analog functions in the transmit
enable or forward mode. The input amplifier (preamp) can be
used single-ended or differentially. If the input is used in the
differential configuration, it is imperative that the input signals be
180 degrees out of phase and of equal amplitudes. This will
ensure proper gain accuracy and harmonic performance. The
preamp stage drives a vernier stage that provides the fine tune
gain adjustment. The approximate step resolution of 0.75 dB is
implemented in this stage and provides a total of approximately
5.25 dB of accumulated attenuation. After the vernier stage, a
DAC provides the bulk of the AD8326’s attenuation (8 bits or
48 dB). The signals in the preamp and vernier gain blocks are
differential to improve the PSRR and linearity. A differential
current is fed from the DAC into the output stage, which
amplifies these currents to the appropriate levels necessary to
drive a 75 Ω load.
The output stage utilizes negative feedback to implement a
differential 75 Ω output impedance, which eliminates the need
for external matching resistors needed in typical video (or
video filter) termination requirements.
SPI ProgrammingThe AD8326 is controlled through a serial peripheral interface
(SPI) of three digital data lines, CLK, DATEN, and SDATA.
Changing the gain requires 8 bits of data to be streamed into the
SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register, Most Significant Bit
(MSB) first, on the rising edge of the CLK pulses. Since a 7-bit
shift register is used in the AD8326, the MSB of the 8-bit word
is a “don’t care” bit and is shifted out of the register on the eighth
clock pulse. The data is latched into the attenuator core on the
rising edge of the DATEN line. This provides control over the
changes in the output signal level. The serial interface timing for
the AD8326 is shown in Figures 2 and 3. The programmable
gain range of the AD8326 is –25.75 dB to +27.5 dB with steps
of 0.75 dB. This provides a total gain range of 53.25 dB. The
AD8326 was characterized with a TOKO transformer (TOKO
#617DB-A0070), and the stated gain values include the losses
due to the transformer.
For gain codes from 0 through 71 the gain transfer function is:
where AV is the gain in dB and CODE is the decimal equivalent
of the 8-bit word. Gain codes 0 to 71 provide linear changes in
gain. Figure 4 shows the gain characteristics of the AD8326 for
all possible values in an 8-bit word. Note that maximum gain is
achieved at Code 71. From Code 72 through 127 the 5.25 dB
of attenuation from the vernier stage is being applied over every
eight codes, resulting in the saw tooth characteristic at the top
of the gain range. Because the eighth bit is shifted out of the
register, the gain characteristics for Codes 128 through 255 are
identical to Codes 0 through 127, as depicted in Figure 4.
Figure 4.Gain Code vs. Gain
Input Bias, Impedance, and TerminationThe VIN+ and VIN– inputs have a dc bias level of approxi-
mately 1.47 V below VCC/2, therefore the input signal should
be ac-coupled using 0.1 μF capacitors as seen in the typical
application circuit (see Figure 5).
The differential input impedance of the AD8326 is approxi-
mately 1600 Ω, while the single-ended input is 800 Ω.
Single-Ended Inverting InputWhen operating the AD8326 in a single-ended input mode VIN+
and VIN– should be terminated as illustrated in Figure 6. On the
AD8326 evaluation boards, this termination method requires the
removal of R12, R13, R14, R16, R17, and R18. Install a 0Ω
jumper at R15, an 82.5 Ω resistor at R10 for a 75 Ω system, and a
39.2 Ω resistor at R11 to balance the inputs of the AD8326
evaluation board (Figure 11). Other input impedance configura-
tions may be calculated using the equations in Figure 6.
Figure 6.Single-Ended Input Impedance
The inverting and noninverting inputs of the AD8326 must be
balanced for all input configurations.
Differential Input from Single-Ended SourceThe default configuration of the evaluation board implements a
Toko 1:1 transformer is included on the board for this purpose
(T3). Enabling the evaluation board for single to differential
input conversion requires R15–R17 to be removed, and 0 Ω
jumpers must be installed on the placeholders for R13, R14, and
R18. For a 75 Ω input impedance, R12 should be 78.7 Ω. Refer
to Figure 11 for evaluation board schematic. In this configuration,
the input signal must be applied to VIN–. Other input imped-
ances may be calculated using the equation in Figure 7.
Figure 7.Differential Signal from Single-Ended Source
Differential Signal SourceThe AD8326 evaluation board is also capable of accepting a
differential input signal. This requires the installation of a 165 Ω
resistor in R12, the removal of R13–R14, R17–R18, and the
installation of 0 Ω jumpers for R15–R16. This configuration
results in a differential input impedance of 150 Ω. Other differ-
ential input impedance configurations may be calculated with
the equation in Figure 8.
Figure 5.Typical Applications Circuit
AD8326
Output Bias, Impedance, and TerminationThe outputs have a dc bias level of approximately VCC/2, there-
fore they should be ac-coupled before being applied to the load.
The differential output impedance of the AD8326 is internally
maintained at 75 Ω, regardless of whether the amplifier is in
transmit enable mode or transmit disable mode, eliminating the
need for external back termination resistors. A 1:1 transformer
is used to couple the amplifier’s differential output to the coaxial
cable while maintaining a proper impedance match. If the out-
put signal is being evaluated on standard 50 Ω test equipment, a
minimum loss 75 Ω–50 Ω pad must be used to provide the test
circuit with proper impedance match.
Single Supply OperationThe 12 V supply should be delivered to each of the VCC pins via
a low impedance power bus to ensure that each pin is at the
same potential. The power bus should be decoupled to ground using
a 10 μF tantalum capacitor located close to the AD8326ARP.
In addition to the 10 μF capacitor, each VCC pin should be
individually decoupled to ground with 0.1 μF ceramic chip
capacitors located close to the pins. The pin labeled BYP (Pin
21) should also be decoupled with a 0.1 μF capacitor. The PCB
should have a low-impedance ground plane covering all unused
portions of the board, except in the area of the input and output
traces in close proximity to the AD8326 and output transformer. All
ground and VEE pins of the AD8326ARP must be connected to
the ground plane to ensure proper grounding of all internal nodes.
Pin 28 and the exposed pad should be connected to ground.
Dual Supply OperationThe +5 V supply power should be delivered to each of the VCC
pins via a low impedance power bus to ensure that each pin is at
the same potential. The –5 V supply should also be delivered to
each of the VEE pins with a low impedance bus. The power buses
should be decoupled to ground with a 10 μF tantalum capacitor
located close to the AD8326ARE. In addition to the 10 μF capaci-
tor, all VCC, VEE and BYP pins should be individually decoupled to
ground with 0.1 μF ceramic chip capacitors located close to the
pins. The PCB should have a low-impedance ground plane
covering all unused portions of the board, except in the area of
the input and output traces in close proximity to the AD8326
and output transformer. All ground pins of the AD8326ARE must
be connected to the ground plane to ensure proper grounding of
all internal nodes. Pin 28 and the exposed thermal pad should
both be tied to ground.
Signal Integrity Layout ConsiderationsCareful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
technique is mandatory. The differential input and output traces
should be kept as short as possible. It is also critical to make
sure that all differential signal paths are symmetrical in length
and width. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8326 in all applications.
Thermal Layout ConsiderationsAs integrated circuits become denser, smaller, and more power-
ful, they often produce more heat. Therefore when designing PC
at +65 dBmV with ±5 V supplies. The AD8326ARP draws a
maximum of 2 W at +67 dBmV with a +12 V supply.
The following guidelines should be used for both the AD8326ARE
and AD8326ARP.
First and foremost, the exposed thermal pad should be soldered
directly to a substantial ground plane that adequately absorbs
heat away from the AD8326 package. This is the simplest, and
most important step in thermally managing the power dissipated in
the AD8326. Increasing the area of copper beneath the AD8326
will lower the thermal resistance in the PCB and more effectively
allow air to remove the heat from the PCB, and consequently,
from the AD8326.
Secondly, thermal stitching is a method for increasing thermal
capacity of the PCB. Additionally, thermal stitching can be used
to provide a thermally efficient area onto which the AD8326
may be soldered. Thermal stitching is accomplished by using a
number of plated through holes (or vias) densely populated in
the solder pad area (but not confined to the size of the TSSOP
or PSOP2 exposed thermal pad). This technique maximizes the
copper area where the package is attached to the PCB increas-
ing the thermal mass or capacity by utilizing more than one
copper plane. This method of thermal management should be
applied in close proximity to the exposed thermal pad.
Another important guideline is to utilize a multilayer PCB with
the AD8326. Lowering the PCB thermal resistance using several
layers will generally increase thermal mass resulting in cooler
junction temperatures.
Using the techniques described above and dedicating 2.9 square
inches of thermally enhanced PCB area, the AD8326 in either
package can operate at safe junction temperatures. Figures 12-17
show the above practices in use on the AD8326ARE-EVAL board.
Initial Power-UpWhen the supply is first applied to the AD8326, the gain setting
of the amplifier is indeterminate. Therefore, as power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0), preventing forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the desired
level by following the procedure in the SPI Programming and
Gain Adjustment section. The TXEN pin can then be brought
from Logic 0 to Logic 1, enabling forward signal transmission at
the desired gain level.
Asynchronous Power-DownThe asynchronous TXEN pin is used to place the AD8326 into
“Between Burst” mode while maintaining a differential output
impedance of 75 Ω. Applying Logic 0 to the TXEN pin acti-
vates the on-chip reverse amplifier, providing a 72% reduction
in consumed power. For 12 V operation, the supply current is
typically reduced from 159 mA to 44 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition
to the TXEN pin, the AD8326 also incorporates an asynchro-
nous SLEEP pin, which may be used to further reduce the supply current
to approximately 4 mA. Applying Logic 0 to the SLEEP pin
places the amplifier into SLEEP mode. Transitioning into or
out of SLEEP mode will result in a transient voltage at the
output of the amplifier.
