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AD8325ARU-REEL
5 V CATV Line Driver Fine Step Output Power Control
REV.0
5 V CATV Line Driver Fine Step
Output Power Control
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 0.75 dB Steps Over a 59.45 dB
Range
Low Distortion at 61 dBmV Output
–57 dBc SFDR at 21 MHz
–55 dBc SFDR at 42 MHz
Output Noise Level
–48 dBmV in 160 kHz
Maintains 75 � Output Impedance
Transmit Enable and Transmit Disable Modes
Upper Bandwidth: 100 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces
APPLICATIONS
Gain-Programmable Line Driver
DOCSIS High-Speed Data Modems
Interactive Cable Set-Top Boxes
PC Plug-in Cable Modems
General-Purpose Digitally Controlled Variable Gain Block
GENERAL DESCRIPTIONThe AD8325 is a low-cost, digitally controlled, variable gain ampli-
fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output gain
over a 59.45 dB range resulting in gain changes of 0.7526 dB/LSB.
The AD8325 comprises a digitally controlled variable attenuator
of 0 dB to –59.45 dB, which is preceded by a low noise, fixed
gain buffer and is followed by a low distortion high power ampli-
fier. The AD8325 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.
Distortion performance of –57 dBc is achieved with an output
level up to 61dBmV at 21MHz bandwidth. A key performance
and cost advantage of the AD8325 results from the ability to
maintain a constant 75Ω output impedance during Transmit
Enable and Transmit Disable conditions. In addition, this
device has a sleep mode function that reduces the quiescent
current to 4mA.
The AD8325 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.
Figure 1.Worst Harmonic Distortion vs. Gain Control
AD8325–SPECIFICATIONS(TA = 25�C, VS = 5 V, RL = 75 �, VIN (differential) = 31 dBmV, VOUT measured through
a 1:1 transformer1 with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.)GAIN CONTROL INTERFACE
OUTPUT CHARACTERISTICS
POWER CONTROL
NOTESTOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.Between Burst Transients measured at the output of a 42 MHz diplexer.
LOGIC INPUTS (TTL/CMOS-Compatible Logic)Logic “1” Current (VINH = 5 V) TXEN
Logic “0” Current (VINL = 0 V) TXEN
Logic “1” Current (VINH = 5 V) SLEEP
TIMING REQUIREMENTSClock Period (TC)
Setup Time SDATA vs. Clock (TDS)
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range)Figure 2.Serial Interface Timing
AD8325
ORDERING GUIDE*Thermal Resistance measured on SEMI standard 4-layer board.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage +VS
Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
TPC 1.Basic Test Circuit
GAIN CONTROL – Decimal
GAIN ERROR
dB
–1.040TPC 2.Gain Error vs. Gain Control
FREQUENCY – MHz
GAIN
dB
0.11001000TPC 3.AC Response
FREQUENCY – MHz
GAIN
dB1001TPC 4.AC Response for Various Cap Loads
TPC 5.Output Referred Noise vs. Gain Control
TPC 6.Isolation in Transmit Disable Mode vs. Frequency
AD8325
FUNDAMENTAL FREQUENCY – MHz
DISTORTION
dBc65TPC 7.Second Order Harmonic Distortion vs. Frequency
for Various Output Levels
FUNDAMENTAL FREQUENCY – MHz
DISTORTION
dBc65
–50TPC 8.Third Order Harmonic Distortion vs. Frequency for
Various Output Levels
GAIN CONTROL – Dec Code
DISTORTION
dBc60
–5080TPC 9.Harmonic Distortion vs. Gain Control
FREQUENCY – MHz
IMPEDANCE
180TPC 10.Input Impedance vs. Frequency
FREQUENCY – MHz
IMPEDANCE 1001TPC 11.Output Impedance vs. Frequency
TPC 12.Adjacent Channel Power
APPLICATIONS
General ApplicationThe AD8325 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (Data Over Cable Service
Interface Specifications) certified cable modems and CATV
set-top boxes. Upstream data is modulated in QPSK or QAM
format, and done with DSP or a dedicated QPSK/QAM modula-
tor. The amplifier receives its input signal from the QPSK/QAM
modulator or from a DAC. In either case the signal must be
low-pass filtered before being applied to the amplifier. Because
the distance from the cable modem to the central office will vary
with each subscriber, the AD8325 must be capable of varying its
output power by applying gain or attenuation to ensure that all
signals arriving at the central office are of the same amplitude.
The upstream signal path contains components such as a trans-
former and diplexer that will result in some amount of power loss.
Therefore, the amplifier must be capable of providing enough
power into a 75 Ω load to overcome these losses without sacri-
ficing the integrity of the output signal.
Operational DescriptionThe AD8325 is composed of four analog functions in the power-
up or forward mode. The input amplifier (preamp) can be used
single-endedly or differentially. If the input is used in the differ-
ential configuration, it is imperative that the input signals are 180
degrees out of phase and of equal amplitudes. This will ensure
proper gain accuracy and harmonic performance. The preamp
stage drives a vernier stage that provides the fine tune gain
adjustment. The 0.7526 dB step resolution is implemented in
the vernier stage and provides a total of approximately 5.25 dB of
attenuation. After the vernier stage, a DAC provides the bulk
of the AD8325’s attenuation (9 bits or 54 dB). The signals in the
preamp and vernier gain blocks are differential to improve the
PSRR and linearity. A differential current is fed from the DAC
into the output stage, which amplifies these currents to the
appropriate levels necessary to drive a 75 Ω load. The output
stage utilizes negative feedback to implement a differential
75 Ω output impedance. This eliminates the need for external
matching resistors needed in typical video (or video filter) ter-
mination requirements.
SPI Programming and Gain AdjustmentGain programming of the AD8325 is accomplished using a
serial peripheral interface (SPI) and three digital control lines,
DATEN, SDATA, and CLK. To change the gain, eight bits
of data are streamed into the serial shift register through the
SDATA port. The SDATA load sequence begins with a falling
edge on the DATEN pin, thus activating the CLK line. With the
CLK line activated, data on the SDATA line is clocked into the
serial shift register Most Significant Bit (MSB) first, on the rising
edge of each CLK pulse. Because only a 7-bit shift register is
used, the MSB of the 8-bit word is a “don’t care” bit and is shifted
out of the register on the eighth clock pulse. A rising edge on
the DATEN line latches the contents of the shift register into
the attenuator core resulting in a well controlled change in the
output signal level. The serial interface timing for the AD8325 is
shown in Figures 2 and 3. The programmable gain range of the
AD8325 is –29.45dB to +30dB and scales 0.7526 dB per least
significant bit (LSB). Because the AD8325 was characterized
with a transformer, the stated gain values already take into account
the losses associated with the transformer.
The gain transfer function is as follows:
AV = 30.0 dB – (0.7526 dB × (79 – CODE)) for 0 ≤ CODE ≤ 79
where AVis the gain in dB and CODE is the decimal equivalent
of the 8-bit word.
Valid gain codes are from 0 to 79. Figure 4 shows the gain char-
acteristics of the AD8325 for all possible values in an 8-bit
word. Note that maximum gain is achieved at Code 79. From
Code 80 through 127, the 5.25 dB of attenuation from the ver-
nier stage is being applied over every eight codes, resulting in
the sawtooth characteristic at the top of the gain range. Because
the eighth bit is a “don’t care” bit, the characteristic for codes 0
through 127 repeats from Codes 128 through 255.
Figure 4.Gain vs. Gain Code
Input Bias, Impedance, and TerminationThe VIN+ and VIN– inputs have a dc bias level of approximately
VCC/2, therefore the input signal should be ac-coupled. The
differential input impedance is approximately 1600 Ω while the
single-ended input impedance is 800 Ω. If the AD8325 is being
operated in a single-ended input configuration with a desired
input impedance of 75Ω, the VIN+ and VIN– inputs should be
terminated as shown in Figure 5. If an input impedance other
than 75Ω is desired, the values of R1 and R2 in Figure 5 can be
Figure 5.Single-Ended Input Termination
AD8325
Output Bias, Impedance, and TerminationThe differential output pins VOUT+ and VOUT– are also biased to a
dc level of approximately VCC/2. Therefore, the outputs should be
ac-coupled before being applied to the load. This is accomplished
with a 1:1 transformer as seen in the typical applications circuit
of Figure 6. The transformer also converts the output signal
from differential to single-ended, while maintaining a proper
impedance match to the line. The differential output impedance
of the AD8325 is internally maintained at 75 Ω, regardless of
whether the amplifier is in transmit enable mode (TXEN = 1)
or transmit disable mode (TXEN = 0). If the output signal is
being evaluated on standard 50 Ω test equipment, a 75Ω to 50 Ω
pad must be used to provide the test circuit with the correct
impedance match.
Power Supply Decoupling, Grounding, and Layout
ConsiderationsCareful attention to printed circuit board layout details will
prevent problems due to associated board parasitics. Proper RF
design techniques are mandatory. The 5 V supply power should be
delivered to each of the VCC pins via a low impedance power bus
to ensure that each pin is at the same potential. The power bus
should be decoupled to ground with a 10 µF tantalum capacitor
located in close proximity to the AD8325. In addition to the
10 µF capacitor, each VCC pin should be individually decoupled to
ground with a 0.1 µF ceramic chip capacitor located as close to
the pin as possible. The pin labeled BYP (Pin 21) should also be
decoupled with a 0.1µF capacitor. The PCB should have a low-
impedance ground plane covering all unused portions of the
component side of the board, except in the area of the input and
output traces (see Figure 10). It is important that all of the
AD8325’s ground pins are connected to the ground plane to
ensure proper grounding of all internal nodes. The differential
input and output traces should be kept as short and symmetrical
as possible. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8325 in all applications.
Initial Power-UpWhen the 5 V supply is first applied to the VCC pins of the
AD8325, the gain setting of the amplifier is indeterminate.
Therefore, as power is first applied to the amplifier, the TXEN
pin should be held low (Logic 0) thus preventing forward signal
transmission. After power has been applied to the amplifier, the
gain can be set to the desired level by following the procedure in
the SPI Programming and Gain Adjustment section. The TXEN
pin can then be brought from Logic 0 to 1, enabling forward
signal transmission at the desired gain level.
Between Burst OperationThe asynchronous TXEN pin is used to place the AD8325 into
“Between Burst” mode while maintaining a differential output
impedance of 75 Ω. Applying a Logic 0 to the TXEN pin acti-
vates the on-chip reverse amplifier, providing a 74% reduction
in consumed power. The supply current is reduced from approxi-
mately 133 mA to approximately 35 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition to
the TXEN pin, the AD8325 also incorporates an asynchronous
SLEEP pin, which may be used to place the amplifier in a high
output impedance state and further reduce the supply current to
approximately 4 mA. Applying a Logic 0 to the SLEEP pin
places the amplifier into SLEEP mode. Transitioning into or
out of SLEEP mode will result in a transient voltage at the output
of the amplifier. Therefore, use only the TXEN pin for DOCSIS
compliant “Between Burst” operation.
Figure 6.Typical Applications Circuit
