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AD8324JRQ
3.3 V Upstream Cable Line Driver
3.3 V Upstream
Cable Line Driver
Rev. 0
FEATURES
Supports DOCSIS 2.0 and Euro-DOCSIS standards for reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output: –59 dBc SFDR at 21 MHz –54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.3 nV/√Hz
Maintains 75 Ω output impedance in TX-enable and
Transmit-disable condition
Upper bandwidth: 100 MHz (full gain range)
3.3 V supply operation
Supports SPI® interfaces
APPLICATIONS
DOCSIS 2.0 and Euro-DOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GENERAL DESCRIPTION The AD83241 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8324
ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications.
The gain of the AD8324 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8324 accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 1:1
transformer.
Distortion performance of –54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quies-
cent current to 30 µA and a full power-down function that
reduces power-down current to 2.5 mA.
The AD8324 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8324 operates from a
single 3.3 V supply.
FUNCTIONAL BLOCK DIAGRAM
VIN+
VIN–
VOUT+
VOUT–
RAMP
GNDDATENDATACLKTXENSLEEP
BYPFigure 1. Functional Block Diagram
FREQUENCY (MHz)
DISTORTION (
Bc)
–4035455565Figure 2. Worst Harmonic Distortion vs. Frequency
Patent pending.
TABLE OF CONTENTS Specifications.....................................................................................3
Logic Inputs (TTL/CMOS Compatible Logic).........................4
Timing Requirements..................................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configurations and Functional Descriptions........................6
Typical Performance Characteristics.............................................7
Applications.....................................................................................10
General Applications..................................................................10
Circuit Description.....................................................................10
Gain Programming for the AD8324........................................10
Input Bias, Impedance, and Termination................................10
Output Bias, Impedance, and Termination.............................10
Power Supply...............................................................................11
Signal Integrity Layout Considerations...................................11
Initial Power-Up.........................................................................11
RAMP Pin and BYP Pin Features............................................11
Power Saving Features...............................................................12
Distortion, Adjacent Channel Power, and DOCSIS...............12
Utilizing Diplex Filters...............................................................12
Noise and DOCSIS.....................................................................12
Evaluation Board Features and Operation..............................13
Differential Signal Source..........................................................13
Differential Signal from Single-Ended Source.......................13
Single-Ended Source..................................................................13
Overshoot on PC Printer Ports................................................14
Installing Visual Basic Control Software.................................14
Running AD8324 Software.......................................................14
Controlling Gain/Attenuation of the AD8324......................14
Transmit Enable and Sleep Mode.............................................14
Memory Functions.....................................................................14
Outline Dimensions.......................................................................16
Ordering Guide..........................................................................16
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
Table 1. TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized
using a 1:1 transformer1 at the device output.
1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz. Guaranteed by design and characterization to ±6 sigma for TA = 25°C.
3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C. Measured through a 1:1 transformer.
5 Specification is worst case over all gain codes. VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2. DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted
TIMING REQUIREMENTS
Table 3. VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted
CLKSDATA
DATEN
TXEN
ANALOG
OUTPUT04339-0-0030
Figure 3. Serial Interface Timing
CLKFigure 4. SDATA Timng
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8324 Stress Ratings Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
TXEN
SDATA
VCC
CLK
VIN+
SLEEP
BYP
VOUT+
NC = NO CONNECT
GND
GND
GND
GND
VIN–
GND
RAMP
VOUT–
GND
VCC04339-0-005
Figure 5. 20-Lead LFCSP Figure 6. 20-Lead QSOP
Table 5. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
DISTORTION (
Bc)
–4035455565Figure 7. Second-Order Harmonic Distortion vs. Frequency
for Various Output Powers
FREQUENCY (MHz)
DISTORTION (
Bc)
–70Figure 8. LFSCP Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
FREQUENCY (MHz)
DISTORTION (
Bc)
–70Figure 9. QSOP Second-Order Harmonic Distortion
FREQUENCY (MHz)
DISTORTION (
Bc)
–4035455565Figure 10. Third-Order Harmonic Distortion vs. Frequency
for Various Output Powers
FREQUENCY (MHz)
DISTORTION (
Bc)
–4035455565Figure 11. LFCSP Third-Order Harmonic Distortion
vs. Frequency vs. Temperature
FREQUENCY (MHz)
DISTORTION (
Bc)
–4035455565Figure 12. QSOP Third-Order Harmonic Distortion
CENTER 21 MHz–100
100 kHz/DIVSPAN 1 MHzOUT
(dBm)
Figure 13. Adjacent Channel Power
FREQUENCY (MHz)
GAIN (
–10Figure 14. AC Response
GAIN CONTROL (Decimal Code)
TPU
STEP SIZE (
0.6Figure 15. Output Step Size vs. Gain Control
FREQUENCY (MHz)
OUT
(dBmV
41.841.942.042.142.242.342.442.5Figure 16. Two-Tone Intermodulation Distortion
FREQUENCY (MHz)
OLATION (dB)
–100Figure 17. Isolation in Transmit Disable Mode vs. Frequency
GAIN CONTROL (Decimal Code)Figure 18. Gain Error vs. Gain Control
