AD8322ARU-AD8322ARU-REEL Fast Delivery |IC PHOENIX CO.,LIMITED

AD8322ARU-REEL ,5 V CATV Line Driver Coarse Step Output Power Controlapplications such as cable@ MAX GAINmodems that are designed to the MCNS-DOCSIS upstream –60standar ..
AD8323 ,5 V CATV Line Driver Fine Stepapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
AD8323ARU ,5 V CATV Line Driver Fine Step Output Power ControlCHARACTERISTICSSpecified AC Voltage Output = 60 dBmV, Max Gain 116 mV p-pNoise Figure Max Gain, f = ..
AD8323ARU ,5 V CATV Line Driver Fine Step Output Power Controlapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
AD8323ARU-REEL ,5 V CATV Line Driver Fine Step Output Power ControlCHARACTERISTICSBandwidth (–3 dB) All Gain Codes 100 MHzBandwidth Roll-Off f = 65 MHz 1.3 dBBandwidt ..
AD8323ARU-REEL ,5 V CATV Line Driver Fine Step Output Power ControlFEATURES FUNCTIONAL BLOCK DIAGRAMSupports DOCSIS Standard for Reverse PathV (7 PINS) BYPCCTransmiss ..
ADP3300ART-2.7 ,0.3-16V; high accuracy anyCAP 50mA low dropout linear regulator. For cellular telephones, notebook, palmtop computers, battery powered systems, PCMCIA regulators, bar code scanners, camcoders, camerasSPECIFICATIONS otherwise noted)Parameter Symbol Conditions Min Typ Max UnitOUTPUT VOLTAGE V V = V 0 ..
ADP3300ART-2.7-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorFEATURES FUNCTIONAL BLOCK DIAGRAMHigh Accuracy Over Line and Load: 0.8% @ 25C,1.4% Over Temperat ..
ADP3300ART-2.7-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorSPECIFICATIONS otherwise noted)Parameter Symbol Conditions Min Typ Max UnitOUTPUT VOLTAGE V V = V 0 ..
ADP3300ART-2.85 ,0.3-16V; high accuracy anyCAP 50mA low dropout linear regulator. For cellular telephones, notebook, palmtop computers, battery powered systems, PCMCIA regulators, bar code scanners, camcoders, camerasSpecifications subject to change without notice.–2– REV. BADP3300ABSOLUTE MAXIMUM RATINGS* PIN FUNC ..
ADP3300ART-3 ,High Accuracy anyCAP 50 mA Low Dropout Linear RegulatorSpecifications subject to change without notice.REV. A–2–ADP3300ABSOLUTE MAXIMUM RATINGS*PIN FUNCTI ..
ADP3300ART-3.2 ,0.3-16V; high accuracy anyCAP 50mA low dropout linear regulator. For cellular telephones, notebook, palmtop computers, battery powered systems, PCMCIA regulators, bar code scanners, camcoders, camerasfeatures an error flag that signals when the device is about toADP3302 (100 mA, Dual Output)lose re ..

AD8322ARU-AD8322ARU-REEL
5 V CATV Line Driver Coarse Step Output Power Control
REV.0
5 V CATV Line Driver
Coarse Step Output Power Control
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 6 dB Steps Over a 42 dB
Range
Low Distortion at 60 dBmV Output
–58 dBc SFDR at 21 MHz
–56 dBc SFDR at 42 MHz
Output Noise Level
–46 dBmV in 160 kHz Bandwidth
Maintains 75 � Output Impedance
Power-Up and Power-Down Condition
180 MHz Bandwidth
5 V Supply Operation
Supports SPI Interfaces
APPLICATIONS
Gain Programmable Line Driver
DOCSIS-Compliant Data Modems
Interactive Set-Top Boxes
PC Plug-in Modems
General-Purpose Digitally Controlled Variable Gain Block
GENERAL DESCRIPTION
The AD8322 is a low-cost, digitally controlled variable gain ampli-
fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output
gain over a 42.14 dB range, with gain steps of 6.02 dB/major
carry.
The AD8322 comprises a digitally controlled variable attenuator
of 0 dB to –42.14 dB, which is preceded by a low-noise, fixed-gain
buffer and is followed by a low-distortion, high-power ampli-
fier. The AD8322 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.
Distortion performance of –58 dBc is achieved with an output level
up to 60 dBmV at 21 MHz bandwidth. A key performance and
cost advantage of the AD8322 results from the ability to maintain
a constant 75 Ω output impedance during power-up and power-
down conditions. This eliminates the need for external 75 Ω
termination resulting in twice the effective output voltage when
compared to a standard operational amplifier.
The AD8322 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.
GAIN CODE – Decimal
DISTORTION
dBc
HD3
HD2
Figure 1.Harmonic Distortion vs. Gain Control
AD8322–SPECIFICATIONS
(TA = 25�C, VS = 5 V, RL = RIN = 75 �, VIN = 92 mV p-p differential, VOUT measured through
a 1:1 transformer1 with insertion loss of 0.5 dB @ 10 MHz unless otherwise noted)
GAIN CONTROL INTERFACE
OUTPUT CHARACTERISTICS
OVERALL PERFORMANCE
POWER SUPPLY
NOTES
1TOKO # 617 DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.
2All distortion measurements taken with differential input signal and represent worst distortion across all gain codes.
3Between burst transients measured at the output of PULSE B5008 42 MHz diplexer.
LOGIC INPUTS (TTL/CMOS Compatible Logic)
Logic “1” Current (VINH = 5 V) PD
TIMING REQUIREMENTS
Clock Period (TC)
Setup Time SDATA vs. Clock (TDS)
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(DATEN, CLK, SDATA, PD, VCC = 5 V: Full Temperature Range)
Figure 2.Serial Interface Timing
Table I. Gain vs. Gain Code
0 = low, 1 = high, x = don’t care.
AD8322
ORDERING GUIDE
*Thermal Resistance measured on SEMI standard 4-layer board.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage +VS
Pins 6, 8, 9, 20, 21, 23, 27 . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Pins 1, 2, 3, 7 . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP (RU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8322 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
GAIN CONTROL – Decimal
GAIN ERROR
dB48163264128
–0.35
TPC 2.Gain Error vs. Gain Control
TPC 3.AC Response vs. Gain Control
1:1
TOKO
617DB-A0070
75�
75�
10�F
0.1�F
+1/2 VIN
–1/2 VIN
0.1�F
DEVICE UNDER TEST
TPC 1.Test Circuit
TPC 4.AC Response for Various Capacitor Loads
TPC 5.Output Noise vs. Gain Code
AD8322
TPC 6.Input Signal Feedthrough vs. Frequency
TPC 7.Second Order Harmonic Distortion vs.
Frequency for Various Output Levels
TPC 8.Third Order Harmonic Distortion vs. Frequency
for Various Output Levels
TPC 9.Input Impedance vs. Frequency (Inputs Shunted
with 432 Ω)
TPC 10.Output Impedance vs. Frequency
APPLICATIONS
General Application
The AD8322 is primarily intended for use as the upstream power
amplifier (PA) in DOCSIS (Data Over Cable Service Interface
Specifications) certified cable modems and CATV set-top boxes.
Upstream data is modulated in QPSK or QAM format. This is
done with DSP or a dedicated QPSK/QAM modulator. The
amplifier receives its input signal from the QPSK/QAM modula-
tor or from a DAC. In either case the signal must be low-pass
filtered before being applied to the amplifier. Because the distance
from the cable modem to the central office will vary with each
subscriber, the AD8322 must be capable of varying its output
power by applying gain or attenuation to ensure that all signals
arriving at the central office are of the same amplitude. The
upstream signal path contains components such as a transformer
and diplexer that will result in some amount of power loss. There-
fore, the amplifier must be capable of providing enough power
into a 75 Ω load to overcome these losses without sacrificing the
integrity of the output signal.
Operational Description
The AD8322 is composed of three analog functions in the power-
up or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differen-
tial configuration, it is imperative that the input signals be 180
degrees out of phase and of equal amplitudes. This will ensure
the proper gain accuracy and harmonic performance. The preamp
stage drives a DAC, which provides the bulk of the AD8322’s
attenuation (7 bits or 42.14 dB). The signals in the preamp and
DAC gain blocks are differential to improve the PSRR and linear-
ity. A differential current is fed from the DAC into the output
stage, which amplifies these currents to the appropriate levels
necessary to drive a 75 Ω load. The output stage utilizes negative
feedback to implement a differential 75 Ω output impedance.
This eliminates the need for external matching resistors.
SPI Programming and Gain Adjustment
Gain programming of the AD8322 is accomplished using a serial
peripheral interface (SPI) and three digital control lines, DATEN,
SDATA, and CLK. To change the gain, eight bits of data are
streamed into the serial shift register through the SDATA port.
The SDATA load sequence begins with a falling edge on the
DATEN pin, thus activating the CLK line. Although the CLK
line is now activated, no change in gain is observed. With the
CLK line activated, data on the SDATA line is clocked into the
serial shift register, Most Significant Bit (MSB) first, on the
rising edge of each CLK pulse. A rising edge on the DATEN line
latches the contents of the shift register into the attenuator core
resulting in a well-controlled change in the output signal level.
The serial interface timing for the AD8322 is shown in Fig-
ures 2 and 3. The programmable gain range of the AD8322 is
–12.64 dB to +29.5 dB and scales 6.02 dB for each major carry.
Because the AD8322 was characterized with a TOKO transformer,
the stated gain values already take into account the losses asso-
ciated with the transformer. Valid gain codes are the major carries
from decimal 1–128 (decimal values 1, 2, 4, 8, 16, 32, 64, 128).
The resulting gain for each code can be seen in Table I. Although
the AD8322 is designed for use with the previous eight codes,
the intermediate codes can be used.
The gain transfer function is as follows:
AV = 20 × LOG (0.2332 × CODE) for 1 ≤ CODE ≤ 128
AV = 29.5 dB for CODE ≥ 128
where AV is the gain in dB and CODE is the decimal equivalent
of the 8-bit word.
Figure 4 shows the gain characteristic for all possible values
(except 0) in an 8-bit word. Code 0 may be used if more
feedthrough isolation is required. It typically provides –85 dB of
isolation across the 5 MHz to 65 MHz upstream band.
GAIN CODE – Decimal
GAIN
dB
–20326496128160192224256
Figure 4.Gain vs. Gain Code
Input Bias, Impedance, and Termination
The VIN+ and VIN– inputs have a dc bias level of approximately
VCC/2, therefore the input signal should be ac-coupled. The
differential input impedance is approximately 235 Ω while the
single-ended input impedance is 210 Ω. If the AD8322 is being
operated in a single-ended input configuration with a desired
input impedance of 75Ω, the VIN+ and VIN– inputs should be
terminated as shown in Figure 5. For input impedances other
than 75Ω, the value of R1 in Figure 5 can be calculated using
the following equation:
Figure 5.Single-Ended Input Termination
AD8322
Output Bias, Impedance, and Termination
The differential output pins VOUT+ and VOUT– are also biased to
a dc level of approximately VCC/2. Therefore, the outputs should
be ac-coupled before being applied to the load. This may be
accomplished by connecting 0.1 µF capacitors in series with the
outputs as shown in the typical applications circuit of Figure 6.
The differential output impedance of the AD8322 is internally
maintained at 75 Ω, regardless of whether the amplifier is in
forward transmit mode or reverse power-down mode, elimi-
nating the need for external back termination resistors. A 1:1
transformer (TOKO #617DB-A0070) is used to couple the
amplifier’s differential output to the coaxial cable while main-
taining a proper impedance match. If the output signal is being
evaluated on standard 50 Ω test equipment, a 75 Ω to 50 Ω
pad must be used to provide the test circuit with the correct
impedance match.
Power Supply Decoupling, Grounding, and Layout
Considerations
Careful attention to printed circuit board layout details will
prevent problems due to associated board parasitics. Proper RF
design technique is mandatory. The 5 V supply power should be
delivered to each of the VCC pins via a low impedance power bus
to ensure that each pin is at the same potential. The power bus
should be decoupled to ground with a 10 µF tantalum capacitor
located in close proximity to the AD8322. In addition to the
10 µF capacitor, each VCC pin should be individually decoupled
to ground with a 0.1 µF ceramic chip capacitor located as close
to the pin as possible. The pin labeled BYP (Pin 5) should also
be decoupled with a 0.1 µF capacitor. The PCB should have a
low impedance ground plane covering all unused portions of the
component side of the board, except in the area of the input and
output traces (see Figure 11). It is important to connect all of
the AD8322 ground pins to ensure proper grounding of all
minimize coupling (crosstalk) through the board. Following these
guidelines will improve the overall performance of the AD8322
in all applications.
Initial Power-Up
When the 5 V supply is first applied to the VCC pins of the
AD8322, the gain setting of the amplifier is indeterminate.
Therefore, as power is first applied to the amplifier, the PD pin
should be held low (Logic 0) thus preventing forward signal
transmission. After power has been applied to the amplifier, the
gain can be set to the desired level by following the procedure in
the SPI Programming and Gain Adjustment section. The PD pin
can then be brought from Logic 0 to 1, enabling forward signal
transmission at the desired gain level.
Asynchronous Power-Down
The asynchronous PD pin is used to place the AD8322 into
“Between Burst” mode while maintaining a differential output
impedance of 75Ω. Applying a Logic 0 to the PD pin activates
the on-chip reverse amplifier, providing a 52% reduction in con-
sumed power. The supply current is reduced from approximately
113mA to approximately 54mA. In this mode of operation,
between burst noise is minimized and the amplifier can no longer
transmit in the upstream direction.
Distortion, Adjacent Channel Power, and DOCSIS
In order to deliver 58 dBmV of high-fidelity output power
required by DOCSIS, the PA should be able to deliver about
60 to 61 dBmV in order to make up for losses associated with the
transformer and diplexer. It should be noted that the AD8322
was characterized with the TOKO 617DB-A0070 transformer.
TPC 7 and TPC 8 show the AD8322 second and third harmonic
distortion performance versus fundamental frequency for vari-
ous output power levels. These figures are useful for determining
the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics
Figure 6.Typical Applications Circuit

Partno	Mfg	Dc	Qty	Available	Descript
AD8322ARU	ADI	N/a	32	avai	5 V CATV Line Driver Coarse Step Output Power Control
AD8322ARU-REEL \|AD8322ARUREEL	AD	N/a	2450	avai	5 V CATV Line Driver Coarse Step Output Power Control