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AD8320ARP
Serial Digital Controlled Variable Gain Line Driver
REV.0
Serial Digital Controlled
Variable Gain Line Driver
FEATURES
8-Bit Serial Gain Control
V/V/LSB Linear Gain Response
36 dB Gain Range
60.20dB Gain Accuracy
Upper Bandwidth: 150 MHz
22 dBm 1 dB Compression Point (75V)
Drives Low Distortion Signals into 75V Load:
–57 dBc SFDR at 42 MHz and 12 dBm Out
–46 dBc SFDR at 42 MHz and 18 dBm Out
Single Supply Operation from 5V to 12V
Maintains 75V Output Impedance
Power-Up and Power-Down Condition
Supports SPI Input Control Standard
APPLICATIONS
Coaxial Cable Driver
HFC Cable Telephony Systems
HFC High Speed Data Modems
Interactive Set-Top Boxes
PC Plug-In Modems
Interfaces with AD9853 I2C Controlled Digital Modulator
High Performance Digitally Controlled Variable Gain
Block
DESCRIPTION
The AD8320 is a digitally controlled variable gain amplifier
optimized for coaxial line driving applications. An 8-bit serial
word determines the desired output gain over a 36dB range
(256 gain levels). The AD8320 provides linear gain response.
The AD8320 is made up of a digitally controlled variable at-
tenuator of 0 dB to –36 dB, which is preceded by a low noise,
fixed gain buffer and followed by a low distortion high power
amplifier. The AD8320 has a 220Ω input impedance and ac-
cepts a single-ended input signal with a specified analog input
level of up to 0.310 V p-p. The output is specified for driving aΩ load, such as coaxial cable, although the AD8320 is ca-
pable of driving other loads. Distortion performance of –57 dBc
is achieved with an output level up to 12dBm (3.1 V p-p) at
42 MHz, while –46 dBc distortion is achieved with an output
level up to 18dBm (6.2V p-p).
A key performance and cost advantage of the AD8320 results
from the ability to maintain a constant 75Ω output impedance
during power-up and power-down conditions. This eliminates
the need for external 75Ω back-termination, resulting in twice
the effective output voltage when compared to a standard opera-
tional amplifier. Additionally, the on-chip 75Ω termination
results in low glitch output during power-down and power-up
transitions, eliminating the need for an external switch.
The AD8320 is packaged in a 20-lead SOIC and operates from
a single +5V through +12V supply and has an operational
temperature range of –40°C to +85°C.
FREQUENCY – MHz10100
DISTORTION – dBc
Figure 1.Worst Harmonic Distortion vs. Frequency for
Various Output Levels at VCC = 12 V
FUNCTIONAL BLOCK DIAGRAM
GNDVCC
VREF
VIN
DATENCLKSDATA
VOUT
AD8320–SPECIFICATIONS
(@ VCC = 12 V, TA = +258C, VIN = 0.310 V p-p, RL = 75V, RS = 75V unless
otherwise noted)
LOGIC INPUTS (TTL/CMOS Logic)
TIMING REQUIREMENTS
Hold Time SDATA vs. Clock (TDH)
TEH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PEDESTAL
CLK
SDATA
DATEN
TON
Figure 2.Serial Interface Timing
(DATEN, CLK, SDATA, 5 V ≤ VCC ≤ 12 V; Full Temperature Range)
(Full Temperature Range, VCC Supply Range, TR = TF = 4 ns, FCLK = 8 MHz unless otherwise noted.)
AD8320
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8320 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
*Shipped in tubes (38 pieces/tube) and dry packed per J-STD-020.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage +VS
Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +13 V
Input Voltages
Pins 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3 V
Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5 V
Internal Power Dissipation
Small Outline (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
GAIN CONTROL – Decimal
GAIN ERROR – dB
0.2
20.3128192256
Figure 4.Gain Error vs. Gain Control
at Various Temperatures
FREQUENCY – Hz
100k1G1M10M100M
GAIN – dB
Figure 7.AC Response
OUTPUT NOISE – nV/
!Hz
GAIN CONTROL – Decimal
064128192256
Figure 10.Output Referred Noise vs.
Gain Control at Various Temperatures
Figure 6.Gain Error vs. Gain Control
at Different Supply Voltages
Figure 9.Input Signal Feedthrough
vs. Frequency
OUTPUT NOISE – nV/
FREQUENCY – Hz
100k1M10M100M
Figure 12.Output Referred Noise vs.
Frequency
GAIN CONTROL – Decimal
GAIN ERROR – dB
0.3
21.264128192256
Figure 5.Gain Error vs. Gain Control
at Various Frequencies
FREQUENCY – Hz
100k1G1M10M100M
GAIN – dB
Figure 8.AC Response
OUTPUT NOISE – nV/
GAIN CONTROL – Decimal
06412819225675
Figure 11.Output Referred Noise vs.
Gain Control at Different Supply
Voltages
AD8320
GAIN CONTROL – Decimal
DISTORTION – dBc64128192256
Figure 13.Worst Harmonic Distor-
tion vs. Gain Control
FREQUENCY – MHz
DISTORTION – dBc
23010100
Figure 16.Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 10 V
HARMONIC DISTORTION 2 dBc
PERCENTAGE
245
244243242241
Figure 19.Distribution of Worst Har-
monic Distortion
FREQUENCY – MHz10100
DISTORTION – dBc
Figure 15.Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 6 V
HARMONIC DISTORTION – dBc
PERCENTAGE
247
Figure 18.Distribution of Worst Har-
monic Distortion
HARMONIC DISTORTION 2 dBc
PERCENTAGE
15.0
30.0
Figure 21.Distribution of Worst Har-
monic Distortion
FREQUENCY – MHz10100
DISTORTION – dBc
Figure 14.Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 5 V
FREQUENCY – MHz10100
DISTORTION – dBc
Figure 17.Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 12 V
HARMONIC DISTORTION 2 dBc
PERCENTAGE
259
258257256255
Figure 20.Distribution of Worst Har-
monic Distortion
TEMPERATURE 2 8C
DISTORTION
dBc
25550100
250225075
Figure 22.Harmonic Distortion vs.
Temperature
Figure 25.Transient Response
OUTPUT VOLTAGE – Volts
TIME – Seconds
Figure 28.Transient Response for
Various Capacitive Loads
Figure 24.Third Order Intercept vs.
Frequency
FREQUENCY – Hz
100k1G1M10M100M
GAIN – dB
Figure 27.AC Response for Various
Capacitive Loads
Figure 30.Transient Response for
Various Capacitive Loads
FREQUENCY – MHz
OUT
– dBm
42.041.242.442.8
Figure 23.Two-Tone Intermodula-
tion Distortion
Figure 26.Transient Response
FREQUENCY – Hz
100k1G1M10M100M
GAIN – dB
Figure 29.AC Response for Various
Capacitive Loads
AD8320
Figure 31.Power-Up/Power-Down
Glitch
Figure 34.Overload Recovery
FREQUENCY – Hz
100k1G1M10M100M
INPUT IMPEDANCE – 70
Figure 37.Input Impedance vs.
Frequency
Figure 33.Overload Recovery
Figure 36.Output Settling Time Due
to Gain Change
TEMPERATURE – 8C
SUPPLY CURRENT – mA
100255075100
Figure 39.Supply Current vs.
Temperature
Figure 32.Clock Feedthrough
Figure 35.Output Settling Time Due
to Input Change
FREQUENCY – Hz
100k1M10M100M
OUTPUT IMPEDANCE –
Figure 38.Output Impedance vs.
Frequency
OPERATIONAL DESCRIPTION
The AD8320 is a digitally controlled variable gain power ampli-
fier that is optimized for driving 75 Ω cable. A multifunctional
bipolar device on single silicon, it incorporates all the analog
features necessary to accommodate reverse path (upstream) high
speed (5MHz to 65MHz) cable data modem and cable tele-
phony requirements. The AD8320 has an overall gain range ofdB (–10dB to 26dB) and is capable of greater than 100MHz
of operation at output signal levels exceeding 18dBm. Overall,
when considering the device’s wide gain range, low distortion,
wide bandwidth and variable load drive, the device can be used
in many variable gain block applications.
The digitally programmable gain is controlled by the three wire
“SPI” compatible inputs. These inputs are called SDATA
(serial data input port), DATEN (data enable low input port)
and CLK (clock input port). See Pin Function Descriptions and
Functional Block diagram. The AD8320 is programmed by an
8-bit “attenuator” word. These eight bits determine the 256
programmable gain settings. See attenuator core description
below. The gain is linear in V/V/LSB and can be described by
the following equation:
AV = 0.316 + 0.077 × Code (RL = 75Ω)
where code is the decimal equivalent of the 8-bit word. For ex-
ample, if all 8 bits are at a logic “1,” the decimal equivalent is
255 and AV equals 19.95 V/V or 26dB. The gain scaling factor
is 0.077V/V/LSB, with an offset of 0.316 V/V (–10.0dB). Fig-
ure 40 shows the linear gain versus decimal code and Figure 41
shows the gain in dB versus decimal code. Note the nonlin-
earity that results when viewed in dB versus code. The dB step
size increases as the attenuation increases (i.e., gain decreases)
and reaches a maximum step size of approximately 1.9dB (gain
change between 01 and 00 decimal).
GAIN – Code – Decimal25632
GAIN – V/V96128160192224
Figure 40.Linear Gain vs. Gain Control
The AD8320 is composed of three analog functions in the power-
up or forward mode (Figure 42). The input inverter/buffer
amplifier provides single-ended to differential output conver-
sion. The output signals are nominally 180 degrees out of phase
and equal in amplitude with a differential voltage gain of 2 (6dB).
Maintaining close to 180 degrees and equal amplitude is re-
quired for proper gain accuracy of the attenuator core over the
Figure 41.Log Gain vs. Gain Control
The attenuator core can be viewed as eight binarily weighted
(differential in–differential out) transconductance (gm) stages
with the “in phase” current outputs of all eight stages connected
in parallel to their respective differential load resistors (not
shown). The core differential output signals are also 180 degrees
out of phase and equal in amplitude. The input stages are like-
wise parallel, connected to the inverting input amplifier and
buffer outputs as shown. Nine bits plus of accuracy is achieved
for all gain settings over the specified frequency, supply voltage
and temperature range. The actual total core GM × RL attenua-
tion is determined by which combination of binarily weighted
gm stages are selected by the data latch. With 8 bits, 256 levels
of attenuation can be programmed. This results in a 36dB
attenuation range (0dB to –36dB). See gain equation above.
GNDVCC
VREF
VIN
DATENCLKSDATA
VOUT
Figure 42.Functional Block Diagram
To update the AD8320 gain, the following digital load sequence
is required. The attenuation setting is determined by the 8-bit
word in the data latch. This 8-bit word is serially loaded (MSB
first) into the shift register at each rising edge of the clock. See
Figure 43. During this data load time (T), DATEN is low and
the data latch is latched holding the previous (T–1) data word
keeping the attenuation level unchanged. After eight clock
cycles the new data word is fully loaded and DATEN is
switched high. This enables the data latch (becomes transpar-
ent) and the loaded register data is passed to the attenuator with
AD8320
GAIN TRANSFER (G2)
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PEDESTAL
CLK
SDATA
DATEN
TON
Figure 43.Serial Interface Timing
what is referred to as sleep and standby modes, and VCC supply
switching via PFETS or equivalent, as described in the applica-
tions section, would be required.
APPLICATIONS
The AD8320 is primarily intended to be used as the return path
(also called upstream path) line driver in cable modem and
cable telephony applications. Data to be transmitted is modu-
lated in either QPSK or QAM format. This is done either in
DSP or by a dedicated QPSK/QAM modulator such as the
AD9853.
The amplifier receives its input signal either from the dedicated
QPSK/QAM modulator or from a DAC. In both cases, the
signal must be low-pass filtered before being applied to the line
driving amplifier.
75V
TO MODEM
RECEIVE
CIRCUITRY
CENTRAL
OFFICESUBSCRIBER
Figure 44.Block Diagram of Cable Modem’s Upstream
Driver Section
The amplifier drives the line through a diplexer. The insertion
loss of a diplexer is typically –3dB. As a result, the line driver
must deliver a power level roughly 3dB greater than required by
the applicable cable modem standard so that diplexer losses are
canceled out.
Because the distance to the central office varies from subscriber
to subscriber, signals from different subscribers will be attenu-
ated by differing amounts. As a result, the line driver is required
to vary its gain so that all signals arriving at the central office
The power amplifier has two basic modes of operation; forward
or power-up mode and reverse or power-down mode. In the
power-up mode (PD = 1), the power amplifier stage is enabled
and the differential output core signal is amplified by 20dB.
With a core attenuation range of 0dB to –36dB and 6dB of
input gain, the overall AD8320 gain range is 26dB to –10dB.
In this mode, the single-ended output signal maintains a dc
level of VCC/2. This dc output level provides for optimum large
signal linearity and allows for dc coupling the output if neces-
sary. The output stage is unique in that it maintains a dynamic
output impedance of 75 Ω. This allows for a direct 75 Ω cable
connection and results in 6dB of added load power versus using
a series 75 Ω back-termination resistor as required with tradi-
tional low output impedance amplifiers. The power amplifier
will also drive lower or higher output loads, although the device’s
gain (not gain range) will change accordingly (see Applications
section).
In the power-down mode (PD = 0), the power amplifier is turned
off and a “reverse” amplifier (the inner triangle in Figure 42) is
enabled. During this 1 to 0 transition, the output power amplifier’s
input stage is also disabled, resulting in no forward output signal
(S21 is 0), although the attenuator core and input amplifier/
buffer signals are not affected (S11 ≈ 0). The function of the
reverse amplifier is to maintain 75 Ω and VCC/2 at the output
port (VOUT) during power-down. This is required to minimize
line reflections (S22 ≈ 0) and ensures proper filter operation for
any forward mode device sharing the same bus (i.e., in a multi-
plexed configuration). (See Applications section.) In the time
domain, as PD switches states, a transitional glitch and pedestal
offset results. (See Figures 31 and 43.) The powered down
supply current drops to 32mA versus 97mA (VCC = 12 V) in
power-up mode.
Generally, using the power-down low input (PD) for switching
allows for multiple devices to be multiplexed via splitters (N-1
off, 1 on) and reduces overall total power consumption as re-

Partno	Mfg	Dc	Qty	Available	Descript
AD8320ARP		N/a	1	avai	Serial Digital Controlled Variable Gain Line Driver