AD8315ARM-REEL ,50 dB GSM PA ControllerSpecifications subject to change without notice.–2– REV. BAD8315Table I. Typical
AD8315ARM-REEL7 ,50 dB GSM PA ControllerSpecifications at Selected Frequencies at 25C (Mean and Sigma) 1 dB Dynamic RangeSlope – mV/dB In ..
AD8315ARMZ , 50 dB GSM PA Controller
AD8315ARMZ , 50 dB GSM PA Controller
AD8316ARM-REEL7 , Dual Output GSM PA Controller
AD8316ARM-REEL7 , Dual Output GSM PA Controller
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3210 ,7-Bit Programmable Multiphase Mobile CPU Synchronous2VID6VID5VID4VID3VID2VID1VID0IREF-+-+ADP3210PIN FUNCTION DESCRIPTIONSPin No. Mnemonic Description1 ..
ADP3211 ,7-Bit, Programmable, Single-Phase, Synchronous Buck Controller3ADP3211, ADP3211APIN FUNCTION DESCRIPTIONSPin No. Mnemonic Description1 PWRGD Power−Good Output. O ..
ADP3211MNR2G , 7-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3211MNR2G , 7-Bit, Programmable, Single-Phase, Synchronous Buck Controller
AD8315ACP-REEL-AD8315ACP-REEL7-AD8315ARM-AD8315ARM.-AD8315ARM-REEL-AD8315ARM-REEL7
50 dB GSM PA Controller
REV. B
50 dB GSM PA Controller
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete RF Detector/Controller Function
>50 dB Range at 0.9 GHz (–49 dBm to +2 dBm re 50 �)
Accurate Scaling from 0.1 GHz to 2.5 GHz
Temperature-Stable Linear-in-dB Response
Log Slope of 23 mV/dB, Intercept at –60 dBm at 0.9 GHz
True Integration Function in Control Loop
Low Power: 20 mW at 2.7 V, 38 mW at 5 V
Power Down to 10.8 �W
APPLICATIONS
Single, Dual, and Triple Band Mobile Handset
(GSM, DCS, EDGE)
Transmitter Power Control
PRODUCT DESCRIPTIONThe AD8315 is a complete low cost subsystem for the precise
control of RF power amplifiers operating in the frequency range
0.1 GHz–2.5 GHz and over a typical dynamic range of 50 dB. It is
intended for use in cellular handsets and other battery-operated
wireless devices. The log amp technique provides a much wider
measurement range and better accuracy than controllers using
diode detectors. In particular, its temperature stability is excellent
over a specified range of –30∞C to +85∞C.
Its high sensitivity allows control at low signal levels, thus reduc-
ing the amount of power that needs to be coupled to the detector.
For convenience, the signal is internally ac-coupled. This
high-pass coupling, with a corner at approximately 0.016 GHz,
determines the lowest operating frequency. Thus, the source
may be dc grounded.
The AD8315 provides a voltage output, VAPC, that has the
voltage range and current drive to directly connect to most hand-
set power amplifiers’ gain control pin. VAPC can swing from 250
mV above ground to within 200 mV below the supply voltage.
Load currents of up to 6 mA can be supported.
The setpoint control input is applied to pin VSET and has an
operating range of 0.25 V–1.4 V. The associated circuit deter-
mines the slope and intercept of the linear-in-dB measurement
system; these are nominally 23 mV/dB and –60 dBm for a 50W
termination (–73 dBV) at 0.9 GHz. Further simplifying the
application of the AD8315, the input resistance of the setpoint
interface is over 100 MW, and the bias current is typically 0.5mA.
The AD8315 is available in MSOP and lead frame chip scale
(LFCSP) packages and consumes 8.5mA from a 2.7V to 5.5V
supply. When powered down, the sleep current is 4mA.
AD8315–SPECIFICATIONS(VS = 2.7 V, T = 25�C, 52.3 � termination on RFIN, unless otherwise noted.)RF INPUT INTERFACE
NOTESOperation down to 0.02 GHz is possible.Mean and Standard Deviation specifications are available in Table I.See TPC 9 for plot of Input Impedance vs. Frequency.This parameter is guaranteed but not tested in production. Limit is –3 sigma from the mean.Response time in a closed-loop system will depend upon the filter capacitor (CFLT) used and the response of the variable gain element.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V
Temporary Overvoltage VPOS
(100 cycles, 2 seconds duration, ENBL Low) . . . . . . .6.3 V
VAPC, VSET, ENBL . . . . . . . . . . . . . . . . . . . . . .0 V, VPOS
RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 dBm
Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . . .1.6 V rms
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .60 mWqJA (MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200∞C/WqJA (LFCSP, Paddle Soldered) . . . . . . . . . . . . . . . . . .80∞C/WqJA (LFCSP, Paddle not Soldered) . . . . . . . . . . . . .200∞C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125∞C
Operating Temperature Range . . . . . . . . . . .–40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec)
MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300∞C
LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
Table I.Typical Specifications at Selected Frequencies at 25�C (Mean and Sigma)
AD8315
–Typical Performance CharacteristicsTPC 1.Input Amplitude vs. VSET
TPC 2.Input Amplitude and Log Conformance vs. VSET at
0.1 GHz
TPC 3.Input Amplitude and Log Conformance vs. VSET at
0.9 GHz
TPC 4.Log Conformance vs. VSET
TPC 5.Input Amplitude and Log Conformance vs. VSET at
1.9 GHz
TPC 6.Input Amplitude and Log Conformance vs. VSET at
2.5 GHz
TPC 8.
Normalization vs. Input Amplitude, 3 Sigma to Either Side
of Mean, 0.9 GHz
AD8315TPC 13.Slope vs. Frequency; –30∞C, +25∞C, and +85∞C
TPC 14.Slope vs. Supply Voltage
TPC 15.AC Response from VSET to VAPC
TPC 16.Intercept vs. Frequency; –30∞C, +25∞C, and +85∞C
TPC 17.Intercept vs. Supply Voltage
TPC 18.VAPC Noise Spectral Density
TPC 19.Maximum VAPC Voltage vs. Supply Voltage by
Load Current
TPC 20.ENBL Response Time
TPC 21.Test Setup for ENBL Response Time
TPC 22.Maximum VAPC Voltage vs. Supply Voltage with
4 mA Load Current
TPC 23.VAPC Response Time, Full-Scale Amplitude
Change, Open-Loop
TPC 24.Test Setup for VAPC Response Time
AD8315TPC 25.Power-On and -Off Response with
VSET Grounded
TPC 26.Test Setup for Power-On and -Off Response with
VSET Grounded
TPC 27.Power-On and -Off Response with VSET and
ENBL Grounded
TPC 28.Test Setup for Power-On and -Off Response with
VSET and ENBL Grounded
GENERAL DESCRIPTION AND THEORYThe AD8315 is a wideband logarithmic amplifier (log amp)
similar in design to the AD8313 and AD8314. However, it is
strictly optimized for use in power control applications rather
than as a measurement device. Figure 1 shows the main features
in block schematic form. The output (Pin 7, VAPC) is intended
to be applied directly to the automatic power-control (APC) pin
of a power amplifier module.
Basic TheoryLogarithmic amplifiers provide a type of compression in which a
signal having a large range of amplitudes is converted to one of
smaller range. The use of the logarithmic function uniquely results
in the output representing the decibel value of the input. The
fundamental mathematical form is:(1)
Here VIN is the input voltage, VZ is called the intercept (voltage)
because when VIN = VZ the argument of the logarithm is unity
and thus the result is zero, and VSLP is called the slope (voltage),
of 24 mV/dB was chosen, and the intercept VZ was placed at the
equivalent of –70 dBV for a sine wave input (316 mV rms). This
corresponds to a power level of –57 dBm when the net resistive
part of the input impedance of the log amp is 50 W. However,
both the slope and the intercept are dependent on frequency (see
TPC 13 and TPC 16).
Keeping in mind that log amps do not respond to power but
only to voltages and that the calibration of the intercept is
waveform dependent and is only quoted for a sine wave signal,
the equivalent power response can be written as:(2)
where the input power PIN and the equivalent intercept PZ are
both expressed in dBm (thus, the quantity in parentheses is
simply a number of decibels), and VDB is the slope expressed as
so many mV/dB. For a log amp having a slope VDB of 24 mV/dB
and an intercept at –57 dBm, the output voltage for an input
power of –30 dBm is 0.024 [–30 – (–57)] = 0.648 V.
Further details about the structure and function of log amps can
be found in data sheets for other log amps produced by Analog
Figure 1.Block Schematic
The intercept need not correspond to a physically realizable part
of the signal range for the log amp. Thus, the specified intercept
is –70 dBV, at 0.1 GHz, whereas the smallest input for accurate
measurement (a +1 dB error, see Table I) at this frequency is
higher, being about –58 dBV. At 2.5 GHz, the +1 dB error point
shifts to –64 dBV. This positioning of the intercept is deliberate
and ensures that the VSET voltage is within the capabilities of cer-
tain DACs, whose outputs cannot swing below 200 mV. Figure2
shows the 100 MHz response of the AD8315; the vertical axis
represents not the output (at pin VAPC) but the value required
at the power control pin VSET to null the control loop. This
will be explained next.
Figure 2.Basic Calibration of the AD8315 at 0.1 GHz
Controller-Mode Log AmpsThe AD8315 combines the two key functions required for the
measurement and control of the power level over a moderately
wide dynamic range. First, it provides the amplification needed to
respond to small signals in a chain of four amplifier/limiter cells
(see Figure 1), each having a small signal gain of 10 dB and a
bandwidth of approximately 3.5 GHz. At the output of each of
these amplifier stages is a full-wave rectifier, essentially a square-
law detector cell that converts the RF signal voltages to a fluctu-
ating current having an average value that increases with signal
level. A further passive detector stage is added before the first
stage. These five detectors are separated by 10 dB, spanning
some 50 dB of dynamic range. Their outputs are each in the
form of a differential current, making summation a simple mat-
ter. It is readily shown that the summed output can closely
approximate a logarithmic function. The overall accuracy at the
extremes of this total range, viewed as the deviation from an
ideal logarithmic response, that is, the log conformance error, can
be judged by reference to TPC 4, which shows that errors across
the central 40 dB are moderate. Other performance curves show
how conformance to an ideal logarithmic function varies with
supply voltage, temperature, and frequency.
In a device intended for measurement applications, this current
would then be converted to an equivalent voltage, to provide the
log(VIN) function shown in Equation 1. However, the design of the
AD8315 differs from standard practice in that its output needs
to be a low noise control voltage for an RF power amplifier, not
a direct measure of the input level. Further, it is highly desirable
that this voltage be proportional to the time-integral of the error
between the actual input VIN and a dc voltage VSET (applied to
Pin 3, VSET) which defines the setpoint, that is, a target value
for the power level, typically generated by a D/A converter.
This is achieved by converting the difference between the sum of
the detector outputs (still in current form) and an internally gener-
ated current proportional to VSET to a single-sided current-mode
signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the
low-pass filter capacitor node), to provide a close approximation
to an exact integration of the error between the power present in
the termination at the input of the AD8315 and the setpoint
voltage. Finally, the voltage developed across the ground-referenced
filter capacitor CFLT is buffered by a special low noise amplifier
of low voltage gain (¥1.35) and presented at Pin 7 (VAPC) for
use as the control voltage for the RF power amplifier. This buffer
can provide “rail-to-rail” swings and can drive a substantial load
current, including large capacitors. Note: The RF power is assumed
to increase monotonically with an increasingly positive delivered
by the amplifier under control of the AD8315 voltage on its
AD8315
Control Loop DynamicsIn order to understand how the AD8315 behaves in a complete
control loop, an expression for the current in the integration
capacitor as a function of the input VIN and the setpoint voltage
VSET must be developed. Refer to Figure 3.
Figure 3.Behavioral Model of the AD8315
First, the summed detector currents are written as a function of
the input:(3)
where IDET is the partially filtered demodulated signal, whose
exact average value will be extracted through the subsequent
integration step; ISLP is the current-mode slope and has a value
of 115 mA per decade (that is, 5.75 mA/dB); VIN is the input in
volts-rms; and VZ is the effective intercept voltage, which, as
previously noted, is dependent on waveform but is 316 mV rms
(–70 dBV) for a sine wave input. Now the current generated by
the setpoint interface is simply:(4)
The difference between this current and IDET is applied to the
loop filter capacitor CFLT. It follows that the voltage appearing on
this capacitor, VFLT, is the time integral of the difference current:(5)(6)
The control output VAPC is slightly greater than this, since the
gain of the output buffer is ¥1.35. Also, an offset voltage is
deliberately introduced in this stage; this is inconsequential
since the integration function implicitly allows for an arbitrary
constant to be added to the form of Equation 6. The polarity is
such that VAPC will rise to its maximum value for any value of
VSET greater than the equivalent value of VIN. In practice, the
VAPC output will rail to the positive supply under this condition
unless the control loop through the power amplifier is present.
In other words, the AD8315 seeks to drive the RF power to its
maximum value whenever it falls below the setpoint. The use
of exact integration results in a final error that is theoretically
zero, and the logarithmic detection law would ideally result in a
constant response time following a step change of either the
setpoint or the power level, if the power-amplifier control
function were likewise linear-in-dB. This latter condition is
rarely true, however, and it follows that in practice, the loop
response time will depend on the power level, and this effect can
strongly influence the design of the control loop.
where VSLP is the volts-per-decade slope from Equation 1, having
a value of 480 mV/decade, and T is an effective time constant for
the integration, being equal to 4.15 kW ¥ CFLT/1.35; the resistor
value comes from the setpoint interface scaling Equation4 and
the factor 1.35 arises because of the voltage gain of the buffer.
So the integration time constant can be written as:(8)
To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function actu-
ally is linear-in-dB. Also use voltages to express the signals at
the power amplifier input and output, for the moment. Let the
RF output voltage be VPA and its input be VCW. Further, to
characterize the gain control function, this form is used:(9)
where GO is the gain of the power amplifier when VAPC = 0 and
VGBC is the gain-scaling. While few amplifiers will conform so
conveniently to this law, it provides a clearer starting point for
understanding the more complex situation that arises when the
gain control law is less ideal.
This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is:
where k is the coupling factor from the output of the power
amplifier to the input of the AD8315 (e.g., ¥0.1 for a “20 dB
coupler”), and TOis a modified time constant (VGBC/VSLP)T.
This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level VSET or the carrier input VCW. Second, it reveals that the
final value of the control voltage VAPC will be determined by
ExampleAssume that the gain magnitude of the power amplifier runs
from a minimum value of ¥0.316 (–10 dB) at VAPC = 0 to ¥100
(40 dB) at VAPC = 2.5 V. Applying Equation 9, GO = 0.316 and
VGBC = 1 V. Using a coupling factor of k = 0.0316 (that is, a
30 dB directional coupler) and recalling that the nominal value of
VSLP is 480 mV and VZ = 316 �V for the AD8315, first calculate
the range of values needed for VSET to control an output range
of 33 dBm to –17 dBm. This can be found by noting that, in
the steady state, the numerator of Equation 7 must be zero,
that is:(12)
when VIN is expanded to kVPA, the fractional voltage sample of
the power amplifier output. Now, for +33 dBm, VPA = 10 V rms,
this evaluates to:
