AD8314ARM-AD8314ARM-REEL-AD8314ARM-REEL7 Fast Delivery |IC PHOENIX CO.,LIMITED

AD8314ARM-REEL ,100 MHz-2500 MHz 45 dB RF Detector/ControllerApplications section of this dataaccuracy than possible using discrete diode detectors. In particul ..
AD8314ARM-REEL ,100 MHz-2500 MHz 45 dB RF Detector/ControllerAPPLICATIONSwhich averaging of the input waveform occurs.Cellular Handsets (TDMA, CDMA, GSM)RSSI an ..
AD8314ARM-REEL7 ,100 MHz-2500 MHz 45 dB RF Detector/ControllerFEATURES For convenience, the signal is internally ac-coupled, using a 5 pFComplete RF Detector/Con ..
AD8314ARMZ ,0.1SPECIFICATIONS S AParameter Conditions Min Typ Max UnitOVERALL FUNCTION1Frequency Range To Meet All ..
AD8314ARMZ-REEL , 100 MHz to 2.7 GHz, 45 dB RF Detector/Controller
AD8314ARMZ-REEL7 ,0.1FEATURES For convenience, the signal is internally ac-coupled, using a 5 pFComplete RF Detector/Con ..
ADP3208C ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..
ADP3208D ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3210 ,7-Bit Programmable Multiphase Mobile CPU Synchronous2VID6VID5VID4VID3VID2VID1VID0IREF-+-+ADP3210PIN FUNCTION DESCRIPTIONSPin No. Mnemonic Description1 ..
ADP3211 ,7-Bit, Programmable, Single-Phase, Synchronous Buck Controller3ADP3211, ADP3211APIN FUNCTION DESCRIPTIONSPin No. Mnemonic Description1 PWRGD Power−Good Output. O ..

AD8314ARM-AD8314ARM-REEL-AD8314ARM-REEL7
100 MHz-2500 MHz 45 dB RF Detector/Controller
REV.0
100 MHz–2500 MHz 45 dB
RF Detector/Controller
FEATURES
Complete RF Detector/Controller Function
Typical Range –58 dBV to –13 dBV
–45 dBm to 0 dBm re 50 V
Frequency Response from 100 MHz to 2.5 GHz
Temperature-Stable Linear-in-dB Response
Accurate to 2.5 GHz
Rapid Response: 70 ns to a 10 dB Step
Low Power: 12 mW at 2.7 V
Power-Down to 20 mA
APPLICATIONS
Cellular Handsets (TDMA, CDMA, GSM)
RSSI and TSSI for Wireless Terminal Devices
Transmitter Power Measurement and Control
PRODUCT DESCRIPTION
The AD8314 is a complete low-cost subsystem for the mea-
surement and control of RF signals in the frequency range
0.1 GHz–2.5 GHz, with a typical dynamic range of 45 dB,
intended for use in a wide variety of cellular handsets and other
wireless devices. It provides a wider dynamic range and better
accuracy than possible using discrete diode detectors. In particular,
its temperature stability is excellent over the full operating range of
–30°C to +85°C.
Its high sensitivity allows control at low power levels, thus
reducing the amount of power that needs to be coupled to the
detector. It is essentially a voltage-responding device, with a
typical signal range of 1.25 mV to 224 mV rms or –58 dBV to
–13 dBV. This is equivalent to –45 dBm to 0 dBm re 50 W.
For convenience, the signal is internally ac-coupled, using a 5 pF
capacitor to a load of 3 kW in shunt with 2 pF. This high-pass
coupling, with a corner at 16 MHz, determines the lowest oper-
ating frequency. Thus, the source may be dc-grounded.
The AD8314 provides two voltage outputs. The first, called
V_UP, increases from close to ground to about 1.2 V as the
input signal level increases from 1.25 mV to 224 mV. This output
is intended for use in measurement mode. Consult the Appli-
cations section of this data sheet for information on use in this
mode. A capacitor may be connected between the V_UP and
FLTR pins when it is desirable to increase the time interval over
which averaging of the input waveform occurs.
The second output, V_DN, is an inversion of V_UP, but with
twice the slope and offset by a fixed amount. This output starts
at about 2.25 V (provided the supply voltage is ‡3.3 V) for
the minimum input and falls to a value close to ground at the
maximum input. This output is intended for analog control
loop applications. A setpoint voltage is applied to VSET and
V_DN is then used to control a VGA or power amplifier. Here
again, an external filter capacitor may be added to extend the
averaging time. Consult the Applications section of this data
sheet for information on use in this mode.
The AD8314 is available in a micro_SOIC package and con-
sumes 4.5 mA from a 2.7 V to 5.5 V supply. When powered
down, the typical sleep current is 20 mA.
FUNCTIONAL BLOCK DIAGRAM
RFIN
COMM
(PADDLE)
VPOS
ENBL
VSETFLTR
AD8314–SPECIFICATIONS(VS = 3 V, TA = +258C, unless otherwise noted)
INPUT INTERFACE
NOTESMean and Standard Deviation speciﬁcations are available in Table I.Increased output possible when using an attenuator between V_UP and VSET to raise the slope.Refer to Figure 19 for details.
Speciﬁcations subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V
V_UP, V_DN, VSET, ENBL . . . . . . . . . . . . . . . .0 V, VPOS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.6 V rms
Equivalent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . .200 mWJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125°C
Operating Temperature Range . . . . . . . . . . .–30°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . .300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section
of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8314 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Pin Function Descriptions
PIN CONFIGURATION
RFIN
ENBL
VSET
VPOSDN
COMMFLTR
ORDERING GUIDE
*Device branded as J5A.
AD8314
INPUT AMPLITUDE – dBV
– Volts
(–52dBm)(–2dBm)
Figure 1. VUP vs. Input Amplitude
INPUT AMPLITUDE – dBV
(–47dBm)
– Volts
(+3dBm)
ERROR – dB
Figure 2. VUP and Log Conformance vs. Input Amplitude at
0.1 GHz; –30°C, +25°C, and +85°C
INPUT AMPLITUDE – dBV
(–47dBm)
– Volts
(+3dBm)
ERROR – dB
Figure 3.VUP and Log Conformance vs. Input Amplitude
at 0.9 GHz; –30°C, +25°C, and +85°C
–Typical Performance Characteristics
Figure 4.Log Conformance vs. Input Amplitude
INPUT AMPLITUDE – dBV
(–47dBm)
– Volts
(+3dBm)
ERROR – dB
Figure 5.VUP and Log Conformance vs. Input Amplitude
at 1.9 GHz; –30°C, +25°C, and +85°C
INPUT AMPLITUDE – dBV
(–47dBm)
– Volts
(+3dBm)
ERROR – dB
Figure 6.VUP and Log Conformance vs. Input Amplitude
at 2.5 GHz; –30°C, +25°C, and +85°C

FREQUENCY – GHz0.5
SLOPE – mV/dB
1.52.02.5
Figure 7.Slope vs. Frequency; –30°C, +25°C, and +85°C

VS – Volts
SLOPE – mV/dB
3.03.54.04.55.05.5
Figure 8.VUP Slope vs. Supply Voltage

FREQUENCY – GHz0.51.0
RESISTANCE –
REACTANCE –
Figure 9.Input Impedance

FREQUENCY – GHz0.51.0
INTERCEPT – dBV
Figure 10.VUP Intercept vs. Frequency: –30°C, +25°C, and
+85°C

VS – Volts
UP
INTERCEPT – dBV
–61
Figure 11.VUP Intercept vs. Supply Voltage

VENBL – Volts
SUPPLY CURRENT – mA
0.40.60.81.01.21.41.61.82.02.22.42.6
Figure 12.Supply Current vs. ENBL Voltage, VS = 3 V
AD8314
VDN GND
VUP GND
VENBL GND
Figure 13.ENBL Response Time
NC = NO CONNECT
–33dBV
Figure 14.Test Setup for ENBL Response Time
Figure 15.AC Response from VSET to V_DN
GND
GND
Figure 16.VUP and VDN Response Time, –40 dBm to 0 dBm
Figure 17.Test Setup for Pulse Response
NOISE SPECTRAL DENSITY –
V/ Hz
FREQUENCY – Hz
1.010k100k1M10M
Figure 18.VDN Noise Spectral Density

VS – Volts
– V
2.82.93.03.13.23.33.43.5
Figure 19.Maximum VDN Voltage vs. VS by Load Current

VDN GND
VUP GND
GND
Figure 20.Power-On and -Off Response, Measurement
Mode
NC = NO CONNECT
732V
–33dBV
Figure 21.Test Setup for Power-On and -Off Response

VS – Volts
– V
2.82.93.03.13.23.33.43.5
Figure 22.Maximum VDN Voltage vs. VS with 3 mA Load

VDN GND
GND
Figure 23.Power-On Response, VDN, Controller Mode with
VSET Held Low
NC = NO CONNECT
+0.2NC
732V
Figure 24.Test Setup for Power-On Response at V_DN
Output, Controller Mode with VSET Pin Held Low
AD8314
Table I.Typical Speciﬁcations at Selected Frequencies at 258C (Mean and Sigma)
*Refer to Figure 29.
GENERAL DESCRIPTION
The AD8314 is a logarithmic ampliﬁer (log amp) similar in
design to the AD8313; further details about the structure and
function may be found in the AD8313 data sheet and other log
amps produced by Analog Devices. Figure 25 shows the main
features of the AD8314 in block schematic form.
The AD8314 combines two key functions needed for the mea-
surement of signal level over a moderately wide dynamic range.
First, it provides the ampliﬁcation needed to respond to small
signals, in a chain of four ampliﬁer/limiter cells, each having
a small-signal gain of 10 dB and a bandwidth of approximately
3.5 GHz. At the output of each of these ampliﬁer stages is a
full-wave rectiﬁer, essentially a square-law detector cell, that
converts the RF signal voltages to a fluctuating current having
an average value that increases with signal level. A further passive
detector stage is added ahead of the ﬁrst stage. Thus, there are
ﬁve detectors, each separated by 10 dB, spanning some 50 dB
of dynamic range. The overall accuracy at the extremes of this
total range, viewed as the deviation from an ideal logarithmic
response, that is, the law-conformance error, can be judged by
reference to Figure 4, which shows that errors across the central
40 dB are moderate. Other curves show how the conformance
to an ideal logarithmic function varies with supply voltage,
temperature and frequency.
The output of these detector cells is in the form of a differential
current, making their summation a simple matter. It can easily
be shown that such summation closely approximates a logarith-
mic function. This result is then converted to a voltage, at pin
V_UP, through a high-gain stage. In measurement modes, this
output is connected back to a voltage-to-current (V–I) stage, in
such a manner that V_UP is a logarithmic measure of the RF input
voltage, with a slope and intercept controlled by the design. For
a ﬁxed termination resistance at the input of the AD8314, a given
voltage corresponds to a certain power level.
RFIN
VPOSDNUP
VSETFLTR
However, in using this part, it must be understood that log amps
do not fundamentally respond to power. It is for this reason that
we use dBV (decibels above 1 V rms) rather than the commonly
used metric of dBm. While the dBV scaling is ﬁxed, independent
of termination impedance, the corresponding power level is not.
For example, 224 mV rms is always –13 dBV (with one further
condition of an assumed sinusoidal waveform; see the Applications
section for more information about the effect of waveform on
logarithmic intercept), and it corresponds to a power of 0dBm
when the net impedance at the input is 50 W. When this imped-
ance is altered to 200 W, the same voltage clearly represents a
power level that is four times smaller (P = V2/R), that is, –6 dBm.
Note that dBV may be converted to dBm for the special case of a
50 W system by simply adding 13 dB (0 dBV is equivalent to
+13dBm).
Thus, the external termination added ahead of the AD8314
determines the effective power scaling. This will often take the
form of a simple resistor (52.3 W will provide a net 50 W input)
but more elaborate matching networks may be used. This im-
pedance determines the logarithmic intercept, the input power
for which the output would cross the baseline (V_UP = zero) if
the function were continuous for all values of input. Since this is
never the case for a practical log amp, the intercept refers to
the value obtained by the minimum-error straight-line ﬁt to the
actual graph of V_UP versus PIN (more generally, VIN). Again,
keep in mind that the quoted values assume a sinusoidal (CW)
signal. Where there is complex modulation, as in CDMA, the
calibration of the power response needs to be adjusted accordingly.
Where a true power (waveform-independent) response is needed,
the use of an rms-responding detector, such as the AD8361,
should be considered.
However, the logarithmic slope, the amount by which the output
V_UP changes for each decibel of input change (voltage or
power) is, in principle, independent of waveform or termination
impedance. In practice, it usually falls off somewhat at higher

Partno	Mfg	Dc	Qty	Available	Descript
AD8314ARM	AD	N/a	4650	avai	100 MHz-2500 MHz 45 dB RF Detector/Controller
AD8314ARM-REEL \|AD8314ARMREEL	ANALOG	N/a	50	avai	100 MHz-2500 MHz 45 dB RF Detector/Controller
AD8314ARM-REEL \|AD8314ARMREEL	AD	N/a	14990	avai	100 MHz-2500 MHz 45 dB RF Detector/Controller
AD8314ARM-REEL7 \|AD8314ARMREEL7	AD	N/a	5265	avai	100 MHz-2500 MHz 45 dB RF Detector/Controller