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AD8314ACP-REEL |AD8314ACPREELADN/a6789avai0.1
AD8314ACP-REEL |AD8314ACPREELN/a5079avai0.1
AD8314ACP-REEL7 |AD8314ACPREEL7ADN/a24000avai0.1
AD8314ACP-REEL7 |AD8314ACPREEL7ADIN/a2248avai0.1
AD8314ACPZ-RL7 |AD8314ACPZRL7ADN/a43avai0.1
AD8314ACPZ-RL7 |AD8314ACPZRL7ANALOGN/a48avai0.1
AD8314ARMZADIN/a12000avai0.1
AD8314ARMZ-REEL7 |AD8314ARMZREEL7ADI-PbN/a123avai0.1


AD8314ACP-REEL7 ,0.1Applications section.2Mean and Standard Deviation specifications are available in Table I.3Increased ..
AD8314ACP-REEL7 ,0.1100 MHz–2.7 GHz 45 dBaRF Detector/Controller*AD8314
AD8314ACPZ-RL7 ,0.1SPECIFICATIONS S AParameter Conditions Min Typ Max UnitOVERALL FUNCTION1Frequency Range To Meet All ..
AD8314ACPZ-RL7 ,0.1Applications section of this dataprovides a wider dynamic range and better accuracy than possiblesh ..
AD8314ARM ,100 MHz-2500 MHz 45 dB RF Detector/ControllerSPECIFICATIONSS AParameter Condition Min Typ Max UnitOVERALL FUNCTIONFrequency Range To Meet All Sp ..
AD8314ARM-REEL ,100 MHz-2500 MHz 45 dB RF Detector/ControllerApplications section of this dataaccuracy than possible using discrete diode detectors. In particul ..
ADP3207CJCPZ-RL , 7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
ADP3208C ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..
ADP3208D ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3210 ,7-Bit Programmable Multiphase Mobile CPU Synchronous2VID6VID5VID4VID3VID2VID1VID0IREF-+-+ADP3210PIN FUNCTION DESCRIPTIONSPin No. Mnemonic Description1 ..


AD8314ACP-REEL-AD8314ACP-REEL7-AD8314ACPZ-RL7-AD8314ARMZ-AD8314ARMZ-REEL7
0.1
REV.A
100 MHz–2.7 GHz 45 dB
RF Detector/Controller
FEATURES
Complete RF Detector/Controller Function
Typical Range –58 dBV to –13 dBV
–45 dBm to 0 dBm re 50 �
Frequency Response from 100 MHz to 2.7 GHz
Temperature-Stable Linear-in-dB Response
Accurate to 2.7 GHz
Rapid Response: 70 ns to a 10 dB Step
Low Power: 12 mW at 2.7 V
Power-Down to 20 �A
APPLICATIONS
Cellular Handsets (TDMA, CDMA, GSM)
RSSI and TSSI for Wireless Terminal Devices
Transmitter Power Measurement and Control
PRODUCT DESCRIPTION

The AD8314 is a complete low cost subsystem for the measure-
ment and control of RF signals in the frequency range of 100 MHz
to 2.7 GHz, with a typical dynamic range of 45 dB, intended for use
in a wide variety of cellular handsets and other wireless devices. It
provides a wider dynamic range and better accuracy than possible
using discrete diode detectors. In particular, its temperature stabil-
ity is excellent over the full operating range of –30°C to +85°C.
Its high sensitivity allows control at low power levels, thus
reducing the amount of power that needs to be coupled to the
detector. It is essentially a voltage-responding device, with a
typical signal range of 1.25 mV to 224 mV rms or –58 dBV to
–13 dBV. This is equivalent to –45 dBm to 0 dBm re 50 Ω.
For convenience, the signal is internally ac-coupled, using a 5 pF
capacitor to a load of 3 kΩ in shunt with 2 pF. This high-pass
coupling, with a corner at approximately 16 MHz, determines the
lowest operating frequency. Thus, the source may be dc-grounded.
The AD8314 provides two voltage outputs. The first, called
V_UP, increases from close to ground to about 1.2 V as the
input signal level increases from 1.25 mV to 224 mV. This output
is intended for use in measurement mode. Consult the Appli-
cations section of this data sheet for information on use in this
mode. A capacitor may be connected between the V_UP and
FLTR pins when it is desirable to increase the time interval over
which averaging of the input waveform occurs.
The second output, V_DN, is an inversion of V_UP, but with
twice the slope and offset by a fixed amount. This output starts
at about 2.25 V (provided the supply voltage is ≥3.3 V) for
the minimum input and falls to a value close to ground at the
maximum input. This output is intended for analog control
loop applications. A setpoint voltage is applied to VSET and
V_DN is then used to control a VGA or power amplifier. Here
again, an external filter capacitor may be added to extend the
averaging time. Consult the Applications section of this data
sheet for information on use in this mode.
The AD8314 is available in micro_SOIC and chip scale packages
and consumes 4.5 mA from a 2.7 V to 5.5 V supply. When pow-
ered down, the typical sleep current is 20 µA.
FUNCTIONAL BLOCK DIAGRAM
AD8314–SPECIFICATIONS(VS = 3 V, TA = 25�C, unless otherwise noted)
INPUT INTERFACE
POWER INTERFACE
NOTESFor a discussion on operation at higher frequencies, see Applications section.Mean and Standard Deviation specifications are available in Table I.Increased output possible when using an attenuator between V_UP and VSET to raise the slope.Refer to TPC 19 for details.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V
V_UP, V_DN, VSET, ENBL . . . . . . . . . . . . . . . .0 V, VPOS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.6 V rms
Equivalent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . .200 mW
θJA (µSO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200°C/W
θJA (CSP, Paddle Soldered) . . . . . . . . . . . . . . . . . . . .80°C/W
θJA (CSP, Paddle not Soldered) . . . . . . . . . . . . . . . .200°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125°C
Operating Temperature Range . . . . . . . . . . .–30°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering 60 sec)
µSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8314 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Pin Function Descriptions
PIN CONFIGURATION
AD8314
INPUT AMPLITUDE – dBV
– Volts
(–52dBm)(–2dBm)

TPC 1. VUP vs. Input Amplitude
INPUT AMPLITUDE – dBV
(–47dBm)
Volts
(+3dBm)
ERROR
dB

TPC 2. VUP and Log Conformance vs. Input
Amplitude at 0.1 GHz; –30°C, +25°C, and +85°C
INPUT AMPLITUDE – dBV
(–47dBm)
Volts
(+3dBm)
ERROR
dB

TPC 3.VUP and Log Conformance vs. Input
Amplitude at 0.9 GHz; –30°C, +25°C, and +85°C
–Typical Performance Characteristics

TPC 4.Log Conformance vs. Input Amplitude
TPC 5.VUP and Log Conformance vs. Input
Amplitude at 1.9 GHz; –30°C, +25°C, and +85°C
INPUT AMPLITUDE – dBV
(–47dBm)
Volts
(+3dBm)
ERROR
dB

TPC 6.VUP and Log Conformance vs. Input
Amplitude at 2.5 GHz; –30°C, +25°C, and +85°C
TPC 7.Slope vs. Frequency; –30°C, +25°C, and +85°C
TPC 8.VUP Slope vs. Supply Voltage
FREQUENCY – GHz0.51.0
RESISTANCE
REACTANCE

TPC 9.Input Impedance
TPC 10.VUP Intercept vs. Frequency: –30°C, +25°C, and
+85°C
VS – Volts
UP
INTERCEPT
dBV
–61

TPC 11.VUP Intercept vs. Supply Voltage
TPC 12.Supply Current vs. ENBL Voltage, VS = 3 V
AD8314
TPC 13.ENBL Response Time
TPC 14.Test Setup for ENBL Response Time
TPC 15.AC Response from VSET to V_DN
TPC 16.VUP and VDN Response Time, –40 dBm
to 0 dBm
TPC 17.Test Setup for Pulse Response
TPC 18.VDN Noise Spectral Density

VS – Volts
2.82.93.03.13.23.33.43.5

TPC 19.Maximum VDN Voltage vs. VS by Load
Current

TPC 20.Power-On and Power-Off Response,
Measurement Mode
TPC 21.Test Setup for Power-On and Power-Off
Response

TPC 22.Maximum VDN Voltage vs. VS with 3 mA
Load
TPC 23.Power-On Response, VDN, Controller
Mode with VSET Held Low
TPC 24.Test Setup for Power-On Response at
V_DN Output, Controller Mode with VSET Pin
Held Low
AD8314
Table I.Typical Specifications at Selected Frequencies at 25�C (Mean and Sigma)

*Refer to Figure 5.
GENERAL DESCRIPTION

The AD8314 is a logarithmic amplifier (log amp) similar in
design to the AD8313; further details about the structure and
function may be found in the AD8313 data sheet and other log
amps produced by Analog Devices. Figure 1 shows the main fea-
tures of the AD8314 in block schematic form.
The AD8314 combines two key functions needed for the mea-
surement of signal level over a moderately wide dynamic range.
First, it provides the amplification needed to respond to small
signals, in a chain of four amplifier/limiter cells, each having
a small-signal gain of 10 dB and a bandwidth of approximately
3.5 GHz. At the output of each of these amplifier stages is a
full-wave rectifier, essentially a square-law detector cell, that
converts the RF signal voltages to a fluctuating current having
an average value that increases with signal level. A further passive
detector stage is added ahead of the first stage. Thus, there are
five detectors, each separated by 10 dB, spanning some 50 dB
of dynamic range. The overall accuracy at the extremes of this
total range, viewed as the deviation from an ideal logarithmic
response, that is, the law-conformance error, can be judged by
reference to TPC 4, which shows that errors across the central
40 dB are moderate. Other curves show how the conformance
to an ideal logarithmic function varies with supply voltage,
temperature and frequency.
The output of these detector cells is in the form of a differential
current, making their summation a simple matter. It can easily
be shown that such summation closely approximates a logarith-
mic function. This result is then converted to a voltage, at pin
V_UP, through a high-gain stage. In measurement modes, this
output is connected back to a voltage-to-current (V–I) stage, in
such a manner that V_UP is a logarithmic measure of the RF input
voltage, with a slope and intercept controlled by the design. For
a fixed termination resistance at the input of the AD8314, a given
voltage corresponds to a certain power level.
However, in using this part, it must be understood that log amps
do not fundamentally respond to power. It is for this reason the
dBV is used (decibels above 1 V rms) rather than the commonly
used metric of dBm. While the dBV scaling is fixed, independent
of termination impedance, the corresponding power level is not.
For example, 224 mV rms is always –13 dBV (with one further
condition of an assumed sinusoidal waveform; see the Applications
section for more information about the effect of waveform on
logarithmic intercept), and it corresponds to a power of 0dBm
when the net impedance at the input is 50 Ω. When this imped-
ance is altered to 200 Ω, the same voltage clearly represents a
power level that is four times smaller (P = V2/R), that is, –6 dBm.
Note that dBV may be converted to dBm for the special case of a
50 Ω system by simply adding 13 dB (0 dBV is equivalent to
+13dBm).
Thus, the external termination added ahead of the AD8314 deter-
mines the effective power scaling. This will often take the form of
a simple resistor (52.3 Ω will provide a net 50 Ω input) but more
elaborate matching networks may be used. This impedance deter-
mines the logarithmic intercept, the input power for which the
output would cross the baseline (V_UP = zero) if the function
were continuous for all values of input. Since this is never the
case for a practical log amp, the intercept refers to the value obtained
by the minimum-error straight-line fit to the actual graph of
V_UP versus PIN (more generally, VIN). Again, keep in mind
that the quoted values assume a sinusoidal (CW) signal. Where
there is complex modulation, as in CDMA, the calibration of
the power response needs to be adjusted accordingly. Where a true
power (waveform-independent) response is needed, the use of
an rms-responding detector, such as the AD8361, should be
considered.
However, the logarithmic slope, the amount by which the output
V_UP changes for each decibel of input change (voltage or
power) is, in principle, independent of waveform or termination
impedance. In practice, it usually falls off somewhat at higher
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